公开(公告)号：US20220169279A1

公开(公告)日：2022-06-02

申请号：US17109508

申请日：2020-12-02

Applicant: Micron Technology, Inc.

Inventor： Amy Rae Griffin ,  Xiao Li ,  Maria Pat F. Chavarria ,  Alpha Chavez Labiano

IPC: B60W60/00 ,  B60W10/30 ,  B60W50/14 ,  G02B7/00 ,  G02B5/30 ,  G05D1/02 ,  G05D1/00

Abstract: Systems, methods, and apparatus related to sensor data processing for a vehicle to improve operation when sunlight or other bright light enters a sensor of the vehicle. In one approach, adjustable filtering is configured for a sensor of a vehicle. In one example, an optical filter is positioned on the path of light that reaches an image sensor of a camera. For example, the filtering improves ability to stay in adaptive cruise control when driving into direct sunlight at sunset. The optical filters can have controllable properties such as polarization. In one example, a controller of the vehicle is configured to automatically adjust the properties of the optical filter to improve image quality to improve object recognition. In another example, a camera is configured with composite vision that uses sensors in different radiation spectrums (e.g., visible light, and infrared light). The composite vision can provide enhanced vision capability for an autonomous vehicle that is driving in the direction of the sun.

公开(公告)号：US20220013434A1

公开(公告)日：2022-01-13

申请号：US17335994

申请日：2021-06-01

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L23/44 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L25/18 ,  H01L23/04 ,  H01L21/50 ,  H01L25/065 ,  H01L23/373 ,  H01L21/52 ,  H01L21/54 ,  H01L23/053 ,  H01L23/31

Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

公开(公告)号：US20210167058A1

公开(公告)日：2021-06-03

申请号：US17068234

申请日：2020-10-12

Applicant: Micron Technology, Inc.

Inventor： Bradley R. Bitz ,  Xiao Li

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/367

Abstract: A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies and a package substrate carrying the first and second semiconductor dies. The second semiconductor die includes a first peripheral portion extending laterally outward beyond a first edge surface of the first semiconductor die. Similarly, the package substrate includes a second peripheral portion extending laterally outward beyond a second edge surface of the second semiconductor die. The semiconductor die assembly further includes a first volume of molded underfill material between the first and second semiconductor dies, a second volume of molded underfill material between the package substrate and the second semiconductor die, a first molded peripheral structure laterally adjacent to the first edge surface of the first semiconductor die, and a second molded peripheral structure laterally adjacent to the second edge surface of the second semiconductor die.

公开(公告)号：US20210167020A1

公开(公告)日：2021-06-03

申请号：US16702222

申请日：2019-12-03

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Lifang Xu ,  Rita J. Klein ,  Xiao Li ,  Everett A. McTeer

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/00 ,  H01L21/768

Abstract: An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.

公开(公告)号：US10916527B2

公开(公告)日：2021-02-09

申请号：US16934924

申请日：2020-07-21

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Anilkumar Chandolu

IPC: H01L25/065 ,  H01L23/367

Abstract: Apparatuses and methods for semiconductor die heat dissipation are described. For example, an apparatus for semiconductor die heat dissipation may include a substrate and a heat spreader. The substrate may include a thermal interface layer disposed on a surface of the substrate, such as disposed between the substrate and the heat spreader. The heat spreader may include a plurality of substrate-facing protrusions in contact with the thermal interface layer, wherein the plurality of substrate-facing protrusions are disposed at least partially through the thermal interface layer.

公开(公告)号：US20190333840A1

公开(公告)日：2019-10-31

申请号：US16505434

申请日：2019-07-08

Applicant: Micron Technology, Inc.

Inventor： Bradley R. Bitz ,  Xiao Li ,  Jaspreet S. Gandhi

IPC: H01L23/42 ,  H01L25/065 ,  H01L23/46 ,  H01L23/427 ,  H01L23/473 ,  H01L23/433

Abstract: Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a base region, at least one second semiconductor die at the base region, and a thermal transfer device attached to the first and second dies. The thermal transfer device includes an encapsulant at least partially surrounding the second die and a via formed in the encapsulant. The encapsulant at least partially defines a cooling channel that is adjacent to a peripheral region of the first die. The via includes a working fluid and/or a solid thermal conductor that at least partially fills the channel.

公开(公告)号：US20190208647A1

公开(公告)日：2019-07-04

申请号：US15862445

申请日：2018-01-04

Applicant: Micron Technology, Inc.

Inventor： Benjamin L. McClain ,  Xiao Li

IPC: H05K3/46 ,  H01L23/00 ,  H01L21/683 ,  H01L23/528 ,  H01L25/065 ,  H01L21/48

Abstract: Semiconductor devices, semiconductor device assemblies, and methods of making such semiconductor devices and semiconductor device assemblies. Material may be removed from a semiconductor device having a first thickness to obtain a second thickness and a carrier may be attached to the semiconductor device having a third thickness with the third thickness plus the second thickness substantially equaling the first thickness. The carrier has a coefficient of thermal expansion (CTE) that differs from the CTE of the semiconductor device. The addition of the carrier to the semiconductor device may change the overall warpage or CTE of a semiconductor device assembly. The semiconductor device assembly be include a redistribution layer between the semiconductor device and a substrate. A material may encapsulate the carrier and the semiconductor device. The carrier may provide electromagnetic shielding. A coating may be applied to external surface of the semiconductor device assembly to provide electromagnetic shielding.

公开(公告)号：US10170389B2

公开(公告)日：2019-01-01

申请号：US14825009

申请日：2015-08-12

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijian Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC: H01L21/00 ,  H01L23/495 ,  H01L23/10 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L23/36 ,  H01L25/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H01L25/065 ,  H01L25/18

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

公开(公告)号：US20160372452A1

公开(公告)日：2016-12-22

申请号：US15254586

申请日：2016-09-01

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L25/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/4882 ,  H01L21/50 ,  H01L21/563 ,  H01L23/04 ,  H01L23/36 ,  H01L23/3675 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/167 ,  H01L2224/16145 ,  H01L2225/06568 ,  H01L2225/06589

Abstract: A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.

公开(公告)号：US20160013114A1

公开(公告)日：2016-01-14

申请号：US14330900

申请日：2014-07-14

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Jaspreet S. Gandhi

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/34 ,  H01L23/10 ,  H01L23/3107 ,  H01L23/3677 ,  H01L23/4275 ,  H01L23/473 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/92125 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1627 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/00012

Abstract: Semiconductor die assemblies having high efficiency thermal paths. In one embodiment, a semiconductor die assembly comprises a package support substrate, a first semiconductor die electrically mounted to the package support substrate, and a plurality of second semiconductor dies. The first die has a stacking site and a peripheral region extending laterally from the stacking site, and the bottom second semiconductor die is attached to the stacking site of the first die. The assembly further includes (a) a thermal transfer structure attached to the peripheral region of the first die that has a cavity in which the second dies are positioned and an inlet, and (b) an underfill material in the cavity. The underfill material has a fillet between the second semiconductor dies caused by injecting the underfill material into the cavity through the inlet port of the casing.

Abstract translation: 具有高效率热路径的半导体管芯组件。 在一个实施例中，半导体管芯组件包括封装支撑衬底，电气安装到封装支撑衬底的第一半导体管芯和多个第二半导体管芯。 第一模具具有堆叠位置和从堆叠位置​​横向延伸的周边区域，并且底部第二半导体管芯附接到第一管芯的堆叠位置。 组件还包括（a）附接到第一模具的周边区域的热转印结构，其具有第二模具所在的空腔和入口，以及（b）空腔中的底部填充材料。 底部填充材料在第二半导体管芯之间具有由底部填充材料通过壳体的入口注入空腔而引起的圆角。