公开(公告)号：US20160267947A1

公开(公告)日：2016-09-15

申请号：US14645446

申请日：2015-03-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: G11C5/06 ,  H01L27/115 ,  H01L21/768 ,  G11C8/10 ,  H01L23/528

CPC classification number: G11C5/063 ,  G11C8/10 ,  G11C8/14 ,  H01L21/768 ,  H01L23/5283 ,  H01L27/11548 ,  H01L27/11575

Abstract: A 3D memory structure and a method for manufactured the same are provided. The 3D memory structure comprises a plurality of strings, a plurality of first conductive lines, a plurality of second conductive lines and a plurality of third conductive lines. The strings are disposed in parallel. The first conductive lines are disposed over the strings. Center regions of the first conductive lines are disposed perpendicular to the strings. The second conductive lines are disposed over the first conductive lines. The second conductive lines connect end regions of half of the first conductive lines. The third conductive lines are disposed over the second conductive lines. The third conductive lines connect end regions of the other half of the first conductive lines.

Abstract translation: 提供了3D存储器结构及其制造方法。 3D存储器结构包括多个串，多个第一导线，多个第二导线和多个第三导线。 琴弦平行放置。 第一导线设置在弦上。 第一导线的中心区域垂直于弦线设置。 第二导线设置在第一导线上。 第二导线连接一半第一导线的端部区域。 第三导线设置在第二导线上。 第三导线连接第一导电线的另一半的端部区域。

公开(公告)号：US20150109844A1

公开(公告)日：2015-04-23

申请号：US14058328

申请日：2013-10-21

Applicant: Macronix International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Chih-Chang Hsieh ,  Chih-Wei Hu

IPC: H01L27/105 ,  G11C7/14 ,  G11C5/06

CPC classification number: G11C7/14 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578

Abstract: An integrated circuit and an operating method for the same are provided. The integrated circuit comprises a stacked structure and a conductive structure. The stacked structure comprises a conductive strip. The conductive structure is disposed above the stacked structure and electrically connected to the conductive strip. The conductive structure and the conductive strip have various gap distances between corresponding points of different pairs according to a basic axis.

Abstract translation: 提供了一种集成电路及其操作方法。 集成电路包括堆叠结构和导电结构。 堆叠结构包括导电条。 导电结构设置在堆叠结构之上并电连接到导电条。 导电结构和导电条根据基本轴线在不同对的对应点之间具有不同的间隙距离。

公开(公告)号：US20140264898A1

公开(公告)日：2014-09-18

申请号：US13948508

申请日：2013-07-23

Applicant: Macronix International Co., Ltd.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/768 ,  H01L21/76838 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/522 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/41766 ,  H01L29/788 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a substrate with a recess, having a bottom and sides, extending into the substrate from the substrate's upper surface. The sides include first and second sides oriented transversely to one another. A stack of alternating active and insulating layers overlie the substrate's surface and the recess. At least some of the active layers have an upper and lower portions extending along upper and lower planes over and generally parallel to the upper surface and to the bottom, respectively. The active layers have first and second upward extensions positioned along the first and second sides to extend from the lower portions of their respective active layers. Conductive strips adjoin the second upward extensions of the said active layers. The conductive strips can comprise sidewall spacers on the sides of the second upward extensions, the conductive strips connected to overlying conductors by interlayer conductors.

Abstract translation: 一种器件包括具有凹陷的基底，具有底部和侧面，从基底的上表面延伸到基底中。 侧面包括横向彼此定向的第一和第二侧面。 交替的有源绝缘层和绝缘层的堆叠覆盖在衬底的表面和凹部上。 活性层中的至少一些具有分别在上表面和下平面上方并且大体上平行于上表面和底部延伸的上部和下部。 有源层具有沿着第一和第二侧定位的第一和第二向上延伸，以从它们各自的有源层的下部延伸。 导电带邻接所述有源层的第二向上延伸。 导电条可以包括在第二向上延伸部分的侧面上的侧壁间隔物，导电条通过层间导体连接到覆盖的导体。

公开(公告)号：US08664761B1

公开(公告)日：2014-03-04

申请号：US13723255

申请日：2012-12-21

Applicant: Macronix International Co., Ltd.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H01L23/48

CPC classification number: H01L21/76831 ,  H01L21/76816 ,  H01L21/76889 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a plurality of stacked structures and a plurality of contact structures. Each of the stacked structures includes a plurality of conductive strips and a plurality of insulating strips, and the conductive strips and the insulating strips are interlaced. Each of the contact structures is electrically connected to each of the stacked structures. The contact structure includes a first conductive pillar, a dielectric material layer, a metal silicide layer, and a second conductive pillar. The dielectric material layer surrounds the lateral surface of the first conductive pillar. The metal silicide layer is formed on an upper surface of the first conductive pillar. The second conductive pillar is formed on the metal silicide layer. The upper surfaces of the first conductive pillars are coplanar.

Abstract translation: 提供了一种半导体结构及其制造方法。 半导体结构包括多个堆叠结构和多个接触结构。 每个堆叠结构包括多个导电条和多个绝缘条，并且导电条和绝缘条是交错的。 每个接触结构电连接到每个堆叠结构。 接触结构包括第一导电柱，介电材料层，金属硅化物层和第二导电柱。 介电材料层围绕第一导电柱的侧表面。 金属硅化物层形成在第一导电柱的上表面上。 第二导电柱形成在金属硅化物层上。 第一导电柱的上表面是共面的。

公开(公告)号：US20250149096A1

公开(公告)日：2025-05-08

申请号：US18504157

申请日：2023-11-08

Applicant: MACRONIX International Co., Ltd.

Inventor： Cheng-Yu Lee ,  Teng-Hao Yeh ,  Hang-Ting Lue

IPC: G11C16/24 ,  G11C5/06 ,  G11C16/08 ,  H10B43/10 ,  H10B43/27

Abstract: A 3D memory including a plurality of tiles, a bit line transistor structure, a first upper conductive layer, and a second upper conductive layer. The bit line transistor structure is disposed between a first sub-tile and a second sub-tile in the plurality of tiles. The first upper conductive layer includes a plurality of local bit lines, a plurality of local source lines and a conductive pattern. The plurality of local bit lines include a first group and a second group of local bit lines separated from each other, wherein two adjacent local bit lines are disposed between adjacent two local source lines. The second upper conductive layer includes a global bit line. The global bit line is electrically connected to the local bit lines through the conductive pattern. The 3D memory could be a 3D AND flash memory with high capacity and high performance.

公开(公告)号：US12260130B2

公开(公告)日：2025-03-25

申请号：US18161900

申请日：2023-01-31

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Teng-Hao Yeh ,  Chih-Chang Hsieh ,  Chun-Hsiung Hung ,  Yung-Chun Li

IPC: G06F17/16 ,  G06F3/06 ,  G06F7/49 ,  G06N3/00 ,  G11C7/06 ,  G11C7/10 ,  G11C7/18 ,  G11C8/14 ,  G11C16/04 ,  G11C16/24 ,  G11C16/28 ,  G11C27/00

Abstract: A memory device for CIM, applicable to a 3D AND-type flash memory, includes a memory array, input word line pairs, and a signal processing circuit. The memory array includes first and second pairs of memory cells. Each first pair of memory cells includes a first memory cell set coupled to a first GBL and a second memory cell set coupled to a second GBL. Each second pair of memory cells includes a third memory cell set coupled to the first GBL and a fourth memory cell set coupled to the second GBL. Each input word line pair includes a first input word line coupled to the first and the second memory cell sets, and a second input word line coupled to the third and the fourth memory cell sets s. The signal processing circuit is coupled to the first and second global bit lines.

公开(公告)号：US12254915B1

公开(公告)日：2025-03-18

申请号：US18240852

申请日：2023-08-31

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Dai-Ying Lee ,  Teng-Hao Yeh ,  Wei-Chen Chen ,  Rachit Dobhal ,  Zefu Zhao ,  Chee-Wee Liu

IPC: G11C11/22 ,  G11C5/06 ,  H10B51/20 ,  H10D30/01 ,  H10D30/69

Abstract: The integrated circuit structure includes a substrate and a memory cell over the substrate. The memory cell includes a channel layer, a first doped region, a second doped region, a first ferroelectric layer, and a first gate layer. The first doped region is at a first side of the channel layer and doped with a first dopant being of a first conductivity type. The second doped region is at a second side of the channel layer opposing the first side and doped with a second dopant being of a second conductivity type different from the first conductivity type. The ferroelectric layer is over the channel layer and between the first and second doped regions. The gate layer is over the ferroelectric layer.

公开(公告)号：US20240170076A1

公开(公告)日：2024-05-23

申请号：US17988773

申请日：2022-11-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Chen-Huan Chen ,  Ken-Hui Chen

IPC: G11C16/34 ,  G11C7/10 ,  G11C16/08 ,  G11C16/24

CPC classification number: G11C16/3459 ,  G11C7/1039 ,  G11C16/08 ,  G11C16/24

Abstract: A memory device, such as a 3D AND flash memory, includes a memory cell block, a word line driver, and a plurality of bit line switches. The word line driver has a plurality of complementary transistor pairs for respectively generating a plurality of word line signals for a plurality of word lines. Substrates of a first transistor and a second transistor of each of the complementary transistor pairs respectively receive a first voltage and a second voltage. Each of the bit line switches includes a third transistor. A substrate of the third transistor receives a third voltage. The first voltage, the second voltage, and the third voltage are constant static voltages during a soft program operation and a soft program verify operation.

公开(公告)号：US20230217655A1

公开(公告)日：2023-07-06

申请号：US17570172

申请日：2022-01-06

Applicant: MACRONIX International Co., Ltd.

Inventor： Cheng-Yu Lee ,  Teng-Hao Yeh

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: A three-dimensional AND flash memory device includes a gate stack structure and a silt. The silt extends along a first direction and divides the gate stack structure into a plurality of sub-blocks. Each sub-block includes a plurality of rows, and each row includes a plurality of channel pillars, a plurality of charge storage structures, and a plurality of pairs of conductive pillars. The plurality of pairs of conductive pillars are arranged in the plurality of channel pillars and penetrate the gate stack structure, and are respectively connected to the plurality of channel pillars. Each pair of conductive pillars includes a first conductive pillar and a second conductive pillar separated from each other along a second direction. There is an acute angle between the second direction and the first direction.

公开(公告)号：US20230082361A1

公开(公告)日：2023-03-16

申请号：US17475932

申请日：2021-09-15

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh ,  Hang-Ting Lue

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A three-dimensional AND flash memory device includes a stack structure, isolators, channel pillars, source pillars and drain pillars, and charge storage structures. The stack structure is located on a dielectric substrate and includes gate layers and insulating layers alternately stacked with each other. The isolators divide the stack structure into sub-blocks and include walls and slits. The walls include isolation layers and the insulating layers stacked alternately with each other, and the isolation layers are buried in the gate layers. The slits alternate with the walls, and each of the slits extends through the stack structure. The channel pillars extend through the stack structure in each of the sub-blocks. The source pillars and the drain pillars are located in the channel pillars. The charge storage structures are located between the gate layers and the channel pillar.