公开(公告)号：US6055199A

公开(公告)日：2000-04-25

申请号：US176880

申请日：1998-10-21

申请人： Kei Hamade ,  Kiyohiro Furutani ,  Takashi Kono ,  Mikio Asakura

发明人： Kei Hamade ,  Kiyohiro Furutani ,  Takashi Kono ,  Mikio Asakura

IPC分类号： G11C29/50 ,  G11C7/00

CPC分类号： G11C29/50 ,  G11C11/401

摘要： A circuit for supplying a stress to memory cells of a semiconductor memory device having the plurality of the memory cells respectively connected to a word line and a bit line comprises a circuit for generating precharge voltage for bit line, a bit line precharging and equalizing circuit which is connected between said circuit for generating precharge voltage for bit line and said memory cells, a pad connected to the bit line precharging and equalizing circuit for applying a desirable voltage to said memory cells through the corresponding bit lines, and a circuit connected to the circuit for generating precharge voltage for bit line for generating a signal for stopping the operation of said circuit for generating precharge voltage for bit line, whereby cell checker patterns can easily be realized in order to screen out possible failures not only in gate oxide films but also in capacitor dielectrics, storage node junctions or the like by applying an arbitrary stress voltage from the outside of the device.

摘要翻译： 用于向具有分别连接到字线和位线的多个存储单元的半导体存储器件的存储单元提供应力的电路包括用于产生位线的预充电电压的电路，位线预充电和均衡电路， 连接在所述用于产生位线的预充电电压的电路和所述存储单元之间，连接到位线预充电和均衡电路的焊盘，用于通过相应的位线向所述存储器单元施加期望的电压，以及连接到电路的电路 用于产生用于产生用于产生用于产生用于产生位线的预充电电压的所述电路的操作的信号的位线的预充电电压，从而可以容易地实现电池检查器图案，以便不仅在栅极氧化膜中屏蔽可能的故障， 电容器电介质，存储节点结等，从外部施加任意的应力电压 设备侧。

公开(公告)号：US5969981A

公开(公告)日：1999-10-19

申请号：US61051

申请日：1998-04-16

申请人： Takashi Kono

发明人： Takashi Kono

IPC分类号： G11C14/00 ,  G11C11/22 ,  G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C11/22

摘要： A memory cell array of a semiconductor memory device is split into memory blocks. A DRAM/nonvolatile mode switching circuit makes each memory cell operate similarly to a DRAM when each memory block is accessed from the exterior while making each memory cell operate as a nonvolatile memory cell to require no refreshment when each memory block is not accessed for a constant period. An internal timer circuit manages a waiting time for the memory block shifting to a nonvolatile mode after entering a non-accessed state. Thus, the semiconductor memory device can attain stable power consumption reduction hardly influenced by a user state.

摘要翻译： 半导体存储器件的存储单元阵列被分成存储块。 当每个存储器块从外部访问时，DRAM /非易失性模式切换电路使得每个存储单元与DRAM类似地操作，同时使每个存储器单元作为非易失性存储器单元操作，以便当每个存储器块不被访问时，不需要刷新 期。 内部定时器电路在进入非访问状态之后管理存储块转移到非易失性模式的等待时间。 因此，半导体存储器件可以实现几乎不受用户状态影响的稳定的功耗降低。

公开(公告)号：US5889657A

公开(公告)日：1999-03-30

申请号：US724002

申请日：1996-09-30

申请人： Takashi Kono

发明人： Takashi Kono

IPC分类号： H01L21/60 ,  H01R4/26 ,  H01R43/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/34 ,  H05K3/40 ,  H01R9/00

CPC分类号： H01R12/57 ,  H05K1/111 ,  H05K3/3442 ,  H01L2224/1411 ,  H01L2224/16237 ,  H01L2224/17107 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01R4/26 ,  H01R43/0235 ,  H01R43/0256 ,  H05K2201/0373 ,  H05K2201/10636 ,  H05K2201/10651 ,  H05K3/3421 ,  H05K3/3431 ,  H05K3/4007 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49147

摘要： A surface-mounting structure of a surface-mounting electronic device onto the surface of a circuit medium is provided. An external terminal of the device has a first mounting surface on which a first set of protrusions are formed. The first mounting surface includes a first uncovered space in the remaining area of the first set of protrusions. A mounting pad of the circuit medium has a second mounting surface on which a second set of protrusions are formed. The second mounting surface includes a second uncovered space in the remaining area of the second set of protrusions. The second mounting surface is opposite to the first mounting surface. The second set of protrusions are inserted into the first uncovered space. The first set of protrusions are inserted into the second uncovered space. A bonding material is placed between the first and second mounting surfaces. The bonding material provides a mechanical engagement between the first and second mounting surfaces, thereby mechanically and electrically connecting the terminal of the device onto the mounting pad of the circuit medium. The mounting process and its process control are simplified, and connection accuracy and reliability are improved.

摘要翻译： 提供了表面安装电子器件在电路介质表面上的表面安装结构。 该装置的外部端子具有形成有第一组突起的第一安装表面。 第一安装表面包括在第一组突起的剩余区域中的第一未覆盖空间。 电路介质的安装垫具有第二安装表面，在其上形成有第二组突起。 第二安装表面包括在第二组突起的剩余区域中的第二未覆盖空间。 第二安装表面与第一安装表面相对。 第二组突起插入第一未覆盖空间。 第一组突起插入第二未覆盖空间。 接合材料放置在第一和第二安装表面之间。 接合材料在第一和第二安装表面之间提供机械接合，从而将器件的端子机械地和电连接到电路介质的安装焊盘上。 安装过程及其过程控制简化，提高了连接精度和可靠性。

公开(公告)号：US08335112B2

公开(公告)日：2012-12-18

申请号：US12766603

申请日：2010-04-23

申请人： Takashi Kono ,  Ken Matsubara ,  Takashi Iwase

发明人： Takashi Kono ,  Ken Matsubara ,  Takashi Iwase

IPC分类号： G11C11/34

CPC分类号： G11C16/26 ,  G11C7/08 ,  G11C8/06 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18

摘要： A nonvolatile semiconductor memory device is provided which can accurately read data with low consumption current. The flash memory selects a memory cell according to an external address signal in response to the leading edge of a clock signal and reads data from the memory cell in response to the leading edge of the clock signal in the normal read mode, whereas, in the low-speed read mode for performing a read operation with lower power consumption than that of the normal read mode, reads data from the memory cell in response to the trailing edge of the clock signal. Therefore, data can be accurately read even if noise is generated in response to the leading edge of the clock signal in the low-speed read mode, because the noise level has dropped at the trailing edge of the clock signal.

摘要翻译： 提供一种非易失性半导体存储器件，其可以以低消耗电流精确地读取数据。 闪速存储器响应于时钟信号的前沿根据外部地址信号选择存储器单元，并且响应于正常读取模式下的时钟信号的前沿从存储器单元读取数据，而在 用于执行具有比正常读取模式更低的功耗的读取操作的低速读取模式，响应于时钟信号的后沿从存储器单元读取数据。 因此，由于噪声电平在时钟信号的后沿已经下降，所以即使在低速读取模式中响应于时钟信号的前沿产生噪声，也可以准确地读取数据。

公开(公告)号：US20100034436A1

公开(公告)日：2010-02-11

申请号：US12431237

申请日：2009-04-28

申请人： Takashi Kono

发明人： Takashi Kono

IPC分类号： G06K9/00

CPC分类号： H04N5/144 ,  A61B1/00009 ,  A61B1/00147 ,  A61B1/041 ,  A61B1/045 ,  A61B5/065 ,  A61B5/073 ,  G06T7/254 ,  G06T2207/10068 ,  G06T2207/30004 ,  H04N2005/2255

摘要： An image processing apparatus includes a motion-vector calculating unit that calculates motion vectors among images taken by an imaging device; a candidate-center calculating unit that calculates candidate centers of a movement of the imaging device and/or candidate centers of a movement of an imaging subject seen on each of the images based on the motion vectors calculated by the motion-vector calculating unit; a reliability calculating unit that calculates a reliability of each of the candidate centers based on a distance between the candidate centers calculated by the candidate-center calculating unit; and a motion-information obtaining unit that obtains information for detecting a motion change among the images taken by the imaging device based on the reliability calculated by the reliability calculating unit.

摘要翻译： 图像处理装置包括运动矢量计算单元，其计算由成像装置拍摄的图像中的运动矢量; 候选中心计算单元，其基于由运动矢量计算单元计算的运动矢量，计算在每个图像上看到的成像装置和/或拍摄对象的移动的候选移动中心的候选中心; 可靠性计算单元，其基于候选中心计算单元计算的候选中心之间的距离来计算每个候选中心的可靠性; 以及运动信息获取单元，其基于由所述可靠性计算单元计算出的可靠度，获得用于检测由所述摄像装置拍摄的图像之间的运动变化的信息。

公开(公告)号：US20090010070A1

公开(公告)日：2009-01-08

申请号：US12149422

申请日：2008-05-01

申请人： Takeshi Kajimoto ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Takashi Kono

发明人： Takeshi Kajimoto ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Takashi Kono

IPC分类号： G11C16/06 ,  G11C7/00

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/3459

摘要： In a flash memory, after an initial write operation ends, each bit line associated with a memory cell subjected to a write is precharged and each bit line associated with a memory cell that is not subjected to the write is discharged and verified to detect a memory cell low in threshold voltage and a memory cell thus detected is subjected to an additional write. The verification can be verified without being affected by a current flowing through the memory cell that is not subjected to the write. All memory cells can have their respective threshold voltages set accurately.

摘要翻译： 在闪速存储器中，在初始写入操作结束后，与经过写入的存储器单元相关联的每个位线被预充电，并且与不经过写入的存储器单元相关联的每个位线被放电并被验证以检测存储器 小区阈值电压和这样检测的存储单元经受附加写入。 可以验证验证，而不受流过不经过写入的存储器单元的电流的影响。 所有存储单元可以准确地设置其各自的阈值电压。

公开(公告)号：US20080285348A1

公开(公告)日：2008-11-20

申请号：US12153927

申请日：2008-05-28

申请人： Takashi Kono ,  Yuichi Kunori ,  Hironori Iga

发明人： Takashi Kono ,  Yuichi Kunori ,  Hironori Iga

IPC分类号： G11C16/24

CPC分类号： G11C16/0491 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/26

摘要： In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line in an upper layer via a switch is adopted, so that charge sharing write-in is carried out between two main bit lines. Accordingly, write-in of data into the flash memory can be carried out with low power consumption, and the threshold voltage can be controlled with precision.

公开(公告)号：US20080239826A1

公开(公告)日：2008-10-02

申请号：US12076787

申请日：2008-03-24

申请人： Tomoya Ogawa ,  Takashi Ito ,  Hidenori Mitani ,  Takashi Kono

发明人： Tomoya Ogawa ,  Takashi Ito ,  Hidenori Mitani ,  Takashi Kono

IPC分类号： G11C16/34

CPC分类号： G11C16/3404

摘要： When a data write sequence is started, initially, write data is latched in a data latch circuit corresponding to one memory mat. Then, a program pulse is applied to the memory mat, and data read from a memory cell, which is a data write target bit in the memory mat, is performed. Thereafter, verify determination of the memory mat is performed. After a verify operation for the memory mat is completed, a program pulse is applied to another memory mat, and a verify operation for another memory mat is performed.

摘要翻译： 当数据写入序列开始时，最初写入数据被锁存在对应于一个存储器垫的数据锁存电路中。 然后，将程序脉冲施加到存储器垫，并且执行从作为存储器垫中的数据写入目标位的存储单元读取的数据。 此后，验证是否执行存储垫的确定。 在存储器垫的验证操作完成之后，将程序脉冲施加到另一个存储器垫，并且执行另一存储器垫的验证操作。

公开(公告)号：US20070019478A1

公开(公告)日：2007-01-25

申请号：US11488621

申请日：2006-07-19

申请人： Takeshi Kajimoto ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Takashi Kono

发明人： Takeshi Kajimoto ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Takashi Kono

IPC分类号： G11C11/34 ,  G11C16/06 ,  G11C16/04

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/3459

摘要： In a flash memory, after an initial write operation ends, each bit line associated with a memory cell subjected to a write is precharged and each bit line associated with a memory cell that is not subjected to the write is discharged and verified to detect a memory cell low in threshold voltage and a memory cell thus detected is subjected to an additional write. The verification can be verified without being affected by a current flowing through the memory cell that is not subjected to the write. All memory cells can have their respective threshold voltages set accurately.

摘要翻译： 在闪速存储器中，在初始写入操作结束后，与经过写入的存储器单元相关联的每个位线被预充电，并且与不经过写入的存储器单元相关联的每个位线被放电并被验证以检测存储器 小区阈值电压和这样检测的存储单元经受附加写入。 可以验证验证，而不受流过不经过写入的存储器单元的电流的影响。 所有存储单元可以准确地设置其各自的阈值电压。

公开(公告)号：US20060270115A1

公开(公告)日：2006-11-30

申请号：US11492541

申请日：2006-07-25

申请人： Mitsunori Sano ,  Takashi Kono ,  Makoto Tsutsui

发明人： Mitsunori Sano ,  Takashi Kono ,  Makoto Tsutsui

IPC分类号： H01L21/00

CPC分类号： H01G9/012 ,  H01G9/042 ,  H01G9/10 ,  H01L2924/0002 ,  Y10S257/924 ,  Y10T29/417 ,  Y10T29/435 ,  Y10T29/4913 ,  H01L2924/00

摘要： In a chip type solid electrolytic capacitor including a capacitor element and a packaging resin covering the capacitor element, the packaging resin has a mount surface and a side surface adjacent to the mount surface. A terminal is electrically connected to the capacitor element and coupled to the packaging resin. The terminal extends along the mount surface and the side surface to have an outer surface exposed from the packaging resin and to have an inner surface opposite to the outer terminal surface. The inner surface has a stepwise shape formed by forging.

摘要翻译： 在包括电容器元件和覆盖电容器元件的封装树脂的芯片型固体电解电容器中，封装树脂具有与安装表面相邻的安装表面和侧表面。 端子电连接到电容器元件并且耦合到封装树脂。 端子沿着安装表面和侧表面延伸以具有从包装树脂露出的外表面并且具有与外端子表面相对的内表面。 内表面具有通过锻造形成的阶梯形状。