公开(公告)号：US06346463B1

公开(公告)日：2002-02-12

申请号：US09565858

申请日：2000-05-05

申请人： Akif Sultan ,  Frederick N. Hause

发明人： Akif Sultan ,  Frederick N. Hause

IPC分类号： H01L2104

CPC分类号： H01L29/1079 ,  H01L21/26513 ,  H01L21/823493

摘要： A method for forming a semiconductor device is provided. A base layer is provided. A first epitaxial layer having a first dopant at a first concentration is formed above the base layer. A second epitaxial layer having a second dopant at a second concentration is formed above the first epitaxial layer. The second concentration is greater than the first concentration. A third epitaxial layer having a third dopant at a third concentration is formed above the second epitaxial layer. The third concentration is less than the second concentration. Ions are implanted in the third epitaxial layer to form an implant region. The implant region is in contact with the second epitaxial layer. A semiconductor device comprises a base layer, first, second, and third epitaxial layers, and an implant region. The first epitaxial layer has a first dopant at a first concentration disposed above the base layer. The second epitaxial layer has a second dopant at a second concentration disposed above the first epitaxial layer. The second concentration is greater than the first concentration. The third epitaxial layer has a third dopant at a third concentration disposed above the second epitaxial layer. The third concentration is less than the second concentration. The implant region is defined in the third epitaxial layer and is in contact with the second epitaxial layer.

摘要翻译： 提供一种形成半导体器件的方法。 提供基层。 具有第一浓度的第一掺杂剂的第一外延层形成在基层之上。 具有第二浓度的第二掺杂剂的第二外延层形成在第一外延层的上方。 第二浓度大于第一浓度。 具有第三浓度的第三掺杂剂的第三外延层形成在第二外延层的上方。 第三浓度小于第二浓度。 将离子注入第三外延层以形成植入区。 注入区域与第二外延层接触。 半导体器件包括基极层，第一，第二和第三外延层以及植入区域。 第一外延层具有设置在基极层之上的第一浓度的第一掺杂剂。 第二外延层具有设置在第一外延层上方的第二浓度的第二掺杂剂。 第二浓度大于第一浓度。 第三外延层具有设置在第二外延层上方的第三浓度的第三掺杂剂。 第三浓度小于第二浓度。 注入区域限定在第三外延层中并且与第二外延层接触。

公开(公告)号：US06255703B1

公开(公告)日：2001-07-03

申请号：US09324462

申请日：1999-06-02

申请人： Frederick N. Hause ,  Manfred Horstmann ,  Karsten Wieczorek

发明人： Frederick N. Hause ,  Manfred Horstmann ,  Karsten Wieczorek

IPC分类号： H01L2976

CPC分类号： H01L29/7833 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28518 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659

摘要： A method is provided for fabricating a semiconductor device on a structure, the method including forming a dielectric layer adjacent a gate conductor of the semiconductor device and above an LDD region of the structure and forming a first dielectric spacer adjacent a first portion of the dielectric layer adjacent the gate conductor and above a second portion of the dielectric layer above the LDD region. The method also includes introducing a dopant into a source/drain region of the structure and removing a third portion of the dielectric layer above the gate conductor, the second portion of the dielectric layer above the LDD region, and the first dielectric spacer. In addition, the method includes forming a first conductive layer above the gate conductor, adjacent the first portion of the dielectric layer and above the LDD region, and saliciding the first conductive layer above the gate conductor and above the LDD region to form a salicided first conductive layer.

摘要翻译： 提供了一种用于在结构上制造半导体器件的方法，该方法包括形成与该半导体器件的栅极导体相邻并且位于该结构的LDD区之上的电介质层，并且形成与该介质层的第一部分相邻的第一电介质间隔物 邻近栅极导体并且位于LDD区域上方的电介质层的第二部分之上。 该方法还包括将掺杂剂引入到该结构的源极/漏极区域中，并且去除栅极导体上方的电介质层的第三部分，在LDD区域上方的电介质层的第二部分和第一电介质间隔物。 此外，该方法包括在栅极导体上方形成第一导电层，邻近电介质层的第一部分并且位于LDD区之上，并且在栅极导体上方和LDD区之上对第一导电层进行水蚀以形成第一 导电层。

公开(公告)号：US06242776B1

公开(公告)日：2001-06-05

申请号：US09324879

申请日：1999-06-02

申请人： Frederick N. Hause ,  Manfred Horstmann ,  Karsten Wieczorek

发明人： Frederick N. Hause ,  Manfred Horstmann ,  Karsten Wieczorek

IPC分类号： H01L2976

CPC分类号： H01L29/66507 ,  H01L29/665 ,  H01L29/6659

摘要： A method is provided for fabricating a semiconductor device on a structure, the method including forming a dielectric layer adjacent a gate conductor of the semiconductor device and above an LDD region of the structure and removing a first portion of the dielectric layer above the gate conductor and above the LDD region. The method also includes forming a first conductive layer above the gate conductor, adjacent the dielectric layer and above the LDD region and saliciding the first conductive layer above the gate conductor and above the LDD region to form a salicided first conductive layer.

摘要翻译： 提供了一种用于在结构上制造半导体器件的方法，该方法包括形成与该半导体器件的栅极导体相邻并且位于该结构的LDD区之上的电介质层，并且去除栅极导体上方的电介质层的第一部分，以及 在LDD地区之上。 该方法还包括在栅极导体上方形成第一导电层，邻近电介质层并在LDD区域上方，并将栅极导体上方的第一导电层和LDD区上方的第一导电层浸水以形成浸渍的第一导电层。

公开(公告)号：US06037232A

公开(公告)日：2000-03-14

申请号：US929697

申请日：1997-09-15

申请人： Karsen Wieczorek ,  Frederick N. Hause

发明人： Karsen Wieczorek ,  Frederick N. Hause

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/417 ,  H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/665 ,  Y10S257/90

摘要： A semiconductor device having an elevated silicidation layer and process for fabricating such a device is provided. Consistent with one embodiment of the invention, at least one gate electrode is formed over a substrate and silicon is formed over at least one active region of the substrate adjacent the gate electrode. A layer of metal is then formed over the silicon. Using the metal layer and the silicon, a silicidation layer is formed over the active region. The active region may, for example, include a source/drain region. The ratio of the depth of the silicidation layer to the depth of the source/drain region may, for example, be greater than or equal to 0.75:1. In other embodiments, the ratio of the silicidation layer depth to source/drain region depth may be greater than or equal to 1:1, 1.5:1 or 2:1.

摘要翻译： 提供了具有提高的硅化物层的半导体器件和用于制造这种器件的工艺。 与本发明的一个实施例一致，在衬底上形成至少一个栅电极，并且在邻近栅电极的衬底的至少一个有源区上形成硅。 然后在硅上形成一层金属。 使用金属层和硅，在有源区上形成硅化层。 有源区可以例如包括源/漏区。 硅化层的深度与源极/漏极区域的深度的比可以例如大于或等于0.75:1。 在其他实施例中，硅化层深度与源/漏区深度的比可以大于或等于1:1,1.5:1或2:1。

公开(公告)号：US06491799B1

公开(公告)日：2002-12-10

申请号：US09766738

申请日：2001-01-22

申请人： Frederick N. Hause ,  Karsten Wieczorek ,  Manfred Horstmann

发明人： Frederick N. Hause ,  Karsten Wieczorek ,  Manfred Horstmann

IPC分类号： C23C1434

CPC分类号： C23C14/10 ,  C23C14/3407 ,  C23C14/3471

摘要： The method disclosed herein comprises initially providing a tool comprised of a process chamber, a lid above the process chamber, an RF coil for assisting in generating a plasma in the chamber, a substrate support, and a power supply coupled to the substrate support. The method continues with the step of positioning a substrate in the tool adjacent the substrate support, introducing a noble gas into the chamber, and forming a layer of material above the substrate by sputtering the lid material by performing at least the following steps: applying approximately 200-300 watts of power to the RF coil at a frequency of approximately 400 KHz and applying approximately 20-60 watts of power to the substrate at a frequency of approximately 13.56 MHz.

摘要翻译： 本文公开的方法包括最初提供一种工具，其包括处理室，处理室上方的盖，用于辅助在室中产生等离子体的RF线圈，衬底支撑件和耦合到衬底支撑件的电源。 该方法继续以下步骤：将衬底定位在邻近衬底支撑件的工具中，将惰性气体引入腔室中，以及通过至少执行以下步骤溅射盖材料在衬底上方形成材料层：近似施加 以大约400KHz的频率向RF线圈施加200-300瓦的功率，并以大约13.56MHz的频率向衬底施加大约20-60瓦的功率。

公开(公告)号：US06218250B1

公开(公告)日：2001-04-17

申请号：US09324183

申请日：1999-06-02

申请人： Frederick N. Hause ,  Karsten Wieczorek ,  Manfred Horstmann

发明人： Frederick N. Hause ,  Karsten Wieczorek ,  Manfred Horstmann

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28518 ,  H01L29/456 ,  H01L29/4933

摘要： A semiconductor device includes a substrate, a gate structure, a plurality of sidewall spacers, and a plurality of first silicide layers. The gate structure is positioned above the substrate. The plurality of sidewall spacers are positioned adjacent to the gate structure. The first silicide layers are positioned in the substrate and have first ends that extend underneath the sidewall spacers. A method for forming a semiconductor device includes forming a gate structure above a substrate. A plurality of sidewall spacers are formed adjacent the gate structure. An implant material is disposed into the substrate using a tilted implantation process that is adapted to form first implant regions in the substrate. The implant regions have first ends that extend underneath the sidewall spacers by a first distance.

摘要翻译： 半导体器件包括衬底，栅极结构，多个侧壁间隔物和多个第一硅化物层。 栅极结构位于衬底上方。 多个侧壁间隔件邻近门结构定位。 第一硅化物层位于衬底中并且具有在侧壁间隔物下方延伸的第一端。 一种形成半导体器件的方法包括在衬底上形成栅极结构。 在栅极结构附近形成多个侧壁间隔物。 使用倾斜的注入工艺将注入材料设置到衬底中，所述倾斜注入工艺适于在衬底中形成第一注入区域。 植入区域具有在侧壁间隔物下方延伸第一距离的第一端。

公开(公告)号：US6133124A

公开(公告)日：2000-10-17

申请号：US245951

申请日：1999-02-05

申请人： Manfred Horstmann ,  Karsten Wieczorek ,  Frederick N. Hause

发明人： Manfred Horstmann ,  Karsten Wieczorek ,  Frederick N. Hause

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/425 ,  H01L21/44

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665

摘要： Various methods of fabricating a silicide layer, and devices incorporating the same are provided. In one aspect, a method of fabricating a silicide layer on a substrate is provided. The method includes the steps of damaging the crystal structure of a portion of the substrate positioned beneath the spacer and depositing a layer of metal on the substrate. The metal layer and the substrate are heated to react the metal with the substrate and form the silicide layer, whereby a portion of the silicide layer extends laterally beneath the spacer. Any unreacted metal is removed. The method enables fabrication of silicide layers with substantial lateral encroachment into LDD structures, resulting in lower possible source-to-drain resistance and enhanced performance for transistors.

摘要翻译： 提供了制造硅化物层的各种方法，以及包含其的装置。 一方面，提供了在基板上制造硅化物层的方法。 该方法包括以下步骤：损坏位于间隔物下方的衬底的一部分的晶体结构并在衬底上沉积金属层。 加热金属层和衬底以使金属与衬底反应并形成硅化物层，由此硅化物层的一部分横向延伸在衬垫下方。 任何未反应的金属被去除。 该方法能够制造具有大量横向侵入LDD结构的硅化物层，导致晶体管的可能的源极 - 漏极电阻和增强的性能。

公开(公告)号：US6060389A

公开(公告)日：2000-05-09

申请号：US75596

申请日：1998-05-11

申请人： William S. Brennan ,  Frederick N. Hause

发明人： William S. Brennan ,  Frederick N. Hause

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/31116 ,  H01L21/76895

摘要： A method for forming a local interconnect coupled to an active area of a semiconductor substrate is provided. The method comprises etching a local interconnect trench into an interlevel dielectric horizontally above the substrate. A titanium layer may be deposited across the semiconductor topography. A TiN diffusion layer is advantageously CVD deposited across the exposed surfaces of the titanium layer. A plasma containing N.sub.2 and H.sub.2 ions is used to bombard the surface of the TiN layer. The resulting TiN layer is conformal and has a low resistivity. A tungsten fill material is then deposited upon the TiN layer to a level above the dielectric. The tungsten adheres well to the TiN layer and is substantially free of voids. The TiN and the tungsten may be removed down to level commensurate with the surface of the dielectric. In this manner a local interconnect is formed electrically coupled to the active area.

摘要翻译： 提供一种用于形成耦合到半导体衬底的有源区域的局部互连的方法。 该方法包括将局部互连沟槽蚀刻成水平地在衬底上方的层间电介质。 钛层可跨越半导体形貌沉积。 TiN扩散层有利地在钛层的暴露表面上CVD沉积。 使用含有N 2和H 2离子的等离子体轰击TiN层的表面。 所得到的TiN层是共形的并且具有低电阻率。 然后将钨填充材料沉积在TiN层上至电介质上方。 钨与TiN层良好粘合，基本上没有空隙。 可以将TiN和钨去除以与电介质的表面相当的水平。 以这种方式，局部互连形成为电耦合到有源区。

公开(公告)号：US6044203A

公开(公告)日：2000-03-28

申请号：US907295

申请日：1997-08-06

申请人： Robert Dawson ,  Frederick N. Hause ,  Charles E. May

发明人： Robert Dawson ,  Frederick N. Hause ,  Charles E. May

IPC分类号： G01J5/02 ,  G01J5/00 ,  G01J5/04 ,  G01J5/60 ,  H01L21/26 ,  H01L21/31 ,  G01J5/06

CPC分类号： G01J5/601 ,  G01J5/041 ,  G01J5/60

摘要： A broadband pyrometer is used for sensing temperature of a semiconductor wafer in an RTA system in association with a monochromator to cancel the backside characteristics of the semiconductor wafer. A rapid thermal anneal (RTA) system includes a rapid thermal anneal (RTA) chamber, a heating lamp arranged in the vicinity of the RTA chamber for heating interior to the RTA chamber, a broadband pyrometer disposed in the vicinity of the RTA chamber and directed to measure interior to the RTA chamber, and a grating monochromator connected to the broadband pyrometer.

摘要翻译： 使用宽带高温计来检测与单色仪相关联的RTA系统中的半导体晶片的温度，以消除半导体晶片的背面特性。 快速热退火（RTA）系统包括快速热退火（RTA）室，布置在RTA室附近的加热灯，用于加热到RTA室内部，宽带高温计设置在RTA室附近并被引导 测量RTA室的内部，以及连接到宽带高温计的光栅单色仪。

公开(公告)号：US5759871A

公开(公告)日：1998-06-02

申请号：US687858

申请日：1996-07-26

申请人： Frederick N. Hause ,  Charles E. May ,  Robert Dawson

发明人： Frederick N. Hause ,  Charles E. May ,  Robert Dawson

IPC分类号： H01L23/544 ,  H01L21/66

CPC分类号： H01L22/34 ,  H01L2924/0002

摘要： A resistor protect mask is used on a shallow trench isolation device junction to cover a device area except for a strip on the perimeter of the device area. The silicide layer formed on the central surface portion of the device and the strip area on the perimeter of the device upon which silicide formation is prevented forms a test structure for evaluation of junction formation that is immune from the effects of silicide formation on a device trench sidewall. Electrical tests and leakage measurements upon the test structure are compared directly to similar silicide shallow trench isolated devices which do not incorporate the resistor protect mask and shallow trench isolated devices without silicide to determine whether salicide processing is a cause of junction effects including junction leakage and short-circuiting.