公开(公告)号：US20050101113A1

公开(公告)日：2005-05-12

申请号：US10704497

申请日：2003-11-06

申请人： Justin Brask ,  Mark Doczy ,  Jack Kavalieros ,  Uday Shah ,  Matthew Metz ,  Robert Chau ,  Robert Turkot

发明人： Justin Brask ,  Mark Doczy ,  Jack Kavalieros ,  Uday Shah ,  Matthew Metz ,  Robert Chau ,  Robert Turkot

IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/3205

CPC分类号： H01L29/4958 ,  H01L21/28079 ,  H01L21/32134 ,  H01L21/823842

摘要： A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, and forming a first metal layer on a first part of the dielectric layer, leaving a second part of the dielectric layer exposed. After a second metal layer is formed on both the first metal layer and the second part of the dielectric layer, a masking layer is formed on the second metal layer.

摘要翻译： 描述制造半导体器件的方法。 该方法包括在衬底上形成电介质层，并且在介电层的第一部分上形成第一金属层，留下介电层的第二部分露出。 在第一金属层和电介质层的第二部分上形成第二金属层之后，在第二金属层上形成掩模层。

公开(公告)号：US20060081932A1

公开(公告)日：2006-04-20

申请号：US11292911

申请日：2005-12-01

申请人： Been-Yih Jin ,  Brian Doyle ,  Scott Hareland ,  Mark Doczy ,  Matthew Metz ,  Boyan Boyanov ,  Suman Datta ,  Jack Kavalieros ,  Robert Chau

发明人： Been-Yih Jin ,  Brian Doyle ,  Scott Hareland ,  Mark Doczy ,  Matthew Metz ,  Boyan Boyanov ,  Suman Datta ,  Jack Kavalieros ,  Robert Chau

IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L29/66772 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76886 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78681

摘要： A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose the substrate; and forming a semiconductor material in the via and in the trench. An apparatus including a device substrate; a dielectric layer formed on a surface of the device substrate; and a device base formed on the dielectric layer including a crystalline structure derived from the device substrate.

公开(公告)号：US20050064616A1

公开(公告)日：2005-03-24

申请号：US10669064

申请日：2003-09-23

申请人： Been-Yih Jin ,  Brian Doyle ,  Scott Hareland ,  Mark Doczy ,  Matthew Metz ,  Boyan Boyanov ,  Suman Datta ,  Jack Kavalieros ,  Robert Chau

发明人： Been-Yih Jin ,  Brian Doyle ,  Scott Hareland ,  Mark Doczy ,  Matthew Metz ,  Boyan Boyanov ,  Suman Datta ,  Jack Kavalieros ,  Robert Chau

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/768 ,  H01L29/786 ,  H01L21/00 ,  H01L21/4763 ,  H01L21/84

CPC分类号： H01L29/66772 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76886 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78681

摘要： A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose the substrate; and forming a semiconductor material in the via and in the trench. An apparatus including a device substrate; a dielectric layer formed on a surface of the device substrate; and a device base formed on the dielectric layer including a crystalline structure derived from the device substrate.

摘要翻译： 一种包括在半导体器件基板上形成通孔电介质层的方法; 在所述通孔电介质层上形成沟槽电介质层; 通过所述沟槽电介质层形成沟槽以暴露所述通孔电介质层; 在所述通孔电介质层中通过所述沟槽形成通孔以暴露所述衬底; 以及在通孔和沟槽中形成半导体材料。 一种装置，包括：装置基板; 形成在所述器件基板的表面上的电介质层; 以及形成在所述电介质层上的器件基底，其包括衍生自所述器件基板的晶体结构。

公开(公告)号：US20060138553A1

公开(公告)日：2006-06-29

申请号：US11362453

申请日：2006-02-24

申请人： Justin Brask ,  Brian Doyle ,  Jack Kavalleros ,  Mark Doczy ,  Uday Shah ,  Robert Chau

发明人： Justin Brask ,  Brian Doyle ,  Jack Kavalleros ,  Mark Doczy ,  Uday Shah ,  Robert Chau

IPC分类号： H01L29/94

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  Y10S438/926 ,  Y10S438/974

摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

公开(公告)号：US20070145468A1

公开(公告)日：2007-06-28

申请号：US11322089

申请日：2005-12-28

申请人： Amlan Majumdar ,  Suman Datta ,  Been-Yih Jin ,  Mark Doczy ,  Robert Chau

发明人： Amlan Majumdar ,  Suman Datta ,  Been-Yih Jin ,  Mark Doczy ,  Robert Chau

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  B82Y10/00 ,  H01L27/115 ,  H01L29/40114 ,  H01L29/42332 ,  H01L29/66825

摘要： Some embodiments of the present invention include apparatuses and methods relating to nonvolatile memory transistors.

摘要翻译： 本发明的一些实施例包括与非易失性存储晶体管相关的装置和方法。

公开(公告)号：US20070138565A1

公开(公告)日：2007-06-21

申请号：US11305452

申请日：2005-12-15

申请人： Suman Datta ,  Mantu Hudait ,  Mark Doczy ,  Jack Kavalleros ,  Majumdar Amlan ,  Justin Brask ,  Been-Yih Jin ,  Matthew Metz ,  Robert Chau

发明人： Suman Datta ,  Mantu Hudait ,  Mark Doczy ,  Jack Kavalleros ,  Majumdar Amlan ,  Justin Brask ,  Been-Yih Jin ,  Matthew Metz ,  Robert Chau

IPC分类号： H01L29/94

CPC分类号： H01L29/7784 ,  H01L21/02178 ,  H01L21/02381 ,  H01L21/02546 ,  H01L21/823807 ,  H01L21/823885 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/15 ,  H01L29/157 ,  H01L29/205 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7783

摘要： A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

摘要翻译： CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。

公开(公告)号：US20050139928A1

公开(公告)日：2005-06-30

申请号：US10748383

申请日：2003-12-29

申请人： Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Scott Hareland ,  Matthew Metz ,  Chris Barns ,  Robert Chau

发明人： Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Scott Hareland ,  Matthew Metz ,  Chris Barns ,  Robert Chau

IPC分类号： H01L21/8238 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/517 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/66545 ,  Y10S438/926

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods comprise providing a substrate comprising a first transistor structure comprising an n-type gate material and second transistor structure comprising a p-type gate material, selectively removing the n-type gate material to form a recess in the first gate structure, and then filling the recess with an n-type metal gate material.

摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法包括提供包括包括n型栅极材料的第一晶体管结构和包括p型栅极材料的第二晶体管结构的衬底，选择性地去除n型栅极材料以在第一栅极结构中形成凹陷，然后 用n型金属栅极材料填充凹部。

公开(公告)号：US20060030104A1

公开(公告)日：2006-02-09

申请号：US11248737

申请日：2005-10-11

申请人： Mark Doczy ,  Justin Brask ,  Steven Keating ,  Chris Barns ,  Brian Doyle ,  Michael McSwiney ,  Jack Kavalieros ,  John Barnak

发明人： Mark Doczy ,  Justin Brask ,  Steven Keating ,  Chris Barns ,  Brian Doyle ,  Michael McSwiney ,  Jack Kavalieros ,  John Barnak

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7833 ,  Y10S438/926

摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

摘要翻译： 至少p型和n型半导体器件沉积在包含金属或金属合金栅极的半导体晶片上。 更具体地，在具有n型和p型金属栅极的半导体晶片上形成互补金属氧化物半导体（CMOS）器件。

公开(公告)号：US20050040469A1

公开(公告)日：2005-02-24

申请号：US10946502

申请日：2004-09-20

申请人： Mark Doczy ,  Justin Brask ,  Steven Keating ,  Chris Barns ,  Brian Doyle ,  Michael McSwiney ,  Jack Kavalieros ,  John Barnak

发明人： Mark Doczy ,  Justin Brask ,  Steven Keating ,  Chris Barns ,  Brian Doyle ,  Michael McSwiney ,  Jack Kavalieros ,  John Barnak

IPC分类号： H01L21/3213 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/66545 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7833 ,  Y10S438/926

摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

摘要翻译： 至少p型和n型半导体器件沉积在包含金属或金属合金栅极的半导体晶片上。 更具体地，在具有n型和p型金属栅极的半导体晶片上形成互补金属氧化物半导体（CMOS）器件。

公开(公告)号：US20080090397A1

公开(公告)日：2008-04-17

申请号：US11986510

申请日：2007-11-21

申请人： Justin Brask ,  Brian Dovle ,  Jack Kavalleros ,  Mark Doczy ,  Uday Shah ,  Robert Chau

发明人： Justin Brask ,  Brian Dovle ,  Jack Kavalleros ,  Mark Doczy ,  Uday Shah ,  Robert Chau

IPC分类号： H01L21/3205

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  Y10S438/926 ,  Y10S438/974

摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

摘要翻译： 要求保护半导体器件，该半导体器件具有形成在绝缘衬底上的具有顶表面和第一和第二横向相对侧壁的半导体本体。 在半导体本体的顶表面和半导体本体的第一和第二横向相对的侧壁上形成栅极电介质。 然后在半导体主体的顶表面上的栅电介质上形成栅电极，并且与半导体本体的第一和第二横向相对的侧壁上的栅电介质相邻。 栅电极包括直接与栅介电层相邻形成的金属膜。 然后在栅电极的相对侧上的半导体本体中形成一对源区和漏区。