中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

256 records (took 0.024 seconds)

    Mixed cross point memory
    81.
    发明授权
    Mixed cross point memory 有权

    公开(公告)号：US10157667B2

    公开(公告)日：2018-12-18

    申请号：US15582321

    申请日：2017-04-28

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Fabio Pellizzer

    IPC: G11C5/06 ,  G11C13/00 ,  G11C11/56

    Abstract: Methods, systems, and devices for multi-deck memory arrays are described. A multi-deck memory device may include a memory array with a cell having a self-selecting memory element and another array with a cell having a memory storage element and a selector device. The device may be programmed to store multiple combinations of logic states using cells of one or more decks. Both the first deck and second deck may be coupled to at least two access lines and may have one access line that is a common access line, coupling the two decks. Additionally, both decks may overlie control circuitry, which facilitates read and write operations. The control circuitry may be configured to write a first state or a second state to one or both of the memory decks via the access lines.

    Apparatuses and methods including memory and operation of same
    82.
    发明授权
    Apparatuses and methods including memory and operation of same 有权

    公开(公告)号：US10134470B2

    公开(公告)日：2018-11-20

    申请号：US14932746

    申请日：2015-11-04

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Stephen Tang ,  Christina Papagianni

    IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56

    Abstract: Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write pulses may program different logic states into the memory cell. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities of the write pulses.

    THREE DIMENSIONAL MEMORY ARRAY
    83.
    发明申请
    THREE DIMENSIONAL MEMORY ARRAY 审中-公开

    公开(公告)号：US20180294312A1

    公开(公告)日：2018-10-11

    申请号：US15482016

    申请日：2017-04-07

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Andrea Redaelli

    IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

    Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.

    METHOD, SYSTEM, AND DEVICE FOR L-SHAPED MEMORY COMPONENT
    84.
    发明申请
    METHOD, SYSTEM, AND DEVICE FOR L-SHAPED MEMORY COMPONENT 审中-公开

    公开(公告)号：US20180145250A1

    公开(公告)日：2018-05-24

    申请号：US15858794

    申请日：2017-12-29

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/124 ,  H01L45/1691

    Abstract: Embodiments disclosed herein may relate to forming reduced size storage components in a cross-point memory array. In an embodiment, a storage cell comprising an L-shaped storage component having an approximately vertical portion extending from a first electrode positioned below the storage material to a second electrode positioned above and/or on the storage component. A storage cell may further comprise a selector material positioned above and/or on the second electrode and a third electrode positioned above and/or on the selector material, wherein the approximately vertical portion of the L-shaped storage component comprises a reduced size storage component in a first dimension.

    CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME
    86.
    发明申请
    CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME 审中-公开

    公开(公告)号：US20170365642A1

    公开(公告)日：2017-12-21

    申请号：US15693102

    申请日：2017-08-31

    Applicant: Micron Technology, Inc.

    Inventor： Marcello Ravasio ,  Samuele Sciarrillo ,  Fabio Pellizzer ,  Innocenzo Tortorelli ,  Roberto Somaschini ,  Cristina Casellato ,  Riccardo Mottadelli

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2463 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

    Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.

    APPARATUSES AND METHODS OF READING MEMORY CELLS BASED ON RESPONSE TO A TEST PULSE
    87.
    发明申请
    APPARATUSES AND METHODS OF READING MEMORY CELLS BASED ON RESPONSE TO A TEST PULSE 审中-公开

    公开(公告)号：US20170309331A1

    公开(公告)日：2017-10-26

    申请号：US15588301

    申请日：2017-05-05

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer

    IPC: G11C13/00 ,  G11C11/56

    CPC classification number: G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0045 ,  G11C2013/0057

    Abstract: The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of reading memory cells in a memory array, such as a cross point memory array. In one aspect, the method comprises providing a memory array comprising a memory cell in one of a plurality of states. The method additionally comprises determining whether a threshold voltage (Vth) of the memory cell has a value within a predetermined read voltage window. A test pulse is applied to the memory cell if it is determined that the threshold voltage has a value within the predetermined read voltage window. The state of the memory cell may be determined based on a response of the memory cell to the test pulse, wherein the state corresponds to the one of the pluralities of states of the memory cell prior to receiving the test pulse.

    Apparatuses and methods of reading memory cells
    89.
    发明授权
    Apparatuses and methods of reading memory cells 有权
    读取存储单元的设备和方法

    公开(公告)号：US09570167B2

    公开(公告)日：2017-02-14

    申请号：US14628824

    申请日：2015-02-23

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer ,  Ferdinando Bedeschi

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0047 ,  G11C2013/0057 ,  G11C2213/72

    Abstract: A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (VTH1) of the memory cell and determining whether the VTH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped VTH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (VTH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the VTH1 and the VTH2.

    Abstract translation: 即使在第一状态分布和第二状态分布之间的重叠阈值电压（VTH）区域中存在阈值电压，也为读取存储器提供了一种方法。 该方法包括首先对存储器单元上的偏置进行斜坡以确定存储器单元的第一阈值电压（VTH1），并确定VTH1是否在重叠的VTH区域内。 当确定存储器单元位于重叠的VTH区域内时，该方法还包括向存储器单元施加写入脉冲; 第二次使存储器单元上的偏置斜坡以确定第二阈值电压（VTH2）; 以及基于VTH1和VTH2之间的比较，在接收到写脉冲之前确定存储单元的状态。

Patent Agency Ranking