公开(公告)号：US10446248B1

公开(公告)日：2019-10-15

申请号：US15959921

申请日：2018-04-23

Applicant: Micron Technology, Inc.

Inventor： Timothy B. Cowles ,  George B. Raad ,  James S. Rehmeyer ,  Jonathan S. Parry

IPC: G11C17/08 ,  G11C17/16 ,  G11C17/18 ,  G11C16/08 ,  G11C16/22 ,  G11C11/22 ,  G11C13/00 ,  G11C11/16

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.

公开(公告)号：US10297307B1

公开(公告)日：2019-05-21

申请号：US15870657

申请日：2018-01-12

Applicant: Micron Technology, Inc.

Inventor： George B. Raad ,  Jonathan S. Parry ,  James S. Rehmeyer ,  Timothy B. Cowles

IPC: G11C7/00 ,  G11C11/406

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

公开(公告)号：US12131040B2

公开(公告)日：2024-10-29

申请号：US17509989

申请日：2021-10-25

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Christopher G. Wieduwilt

IPC: G11C5/06 ,  G06F3/06 ,  G11C17/16

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C5/063 ,  G11C17/165

Abstract: Signaling indicative of a command to initialize a plurality of memory dies of a memory device can be received by the memory device. Initialization of a memory die of the memory device can be delayed, at the memory die and based at least in part on fuse states of an array of fuses of the memory die, by an amount of time relative to receipt of the signaling by the memory device. Delaying initialization of memory dies of the memory device in a staggered or asynchronous manner can evenly distribute power consumption of the memory dies so that the likelihood of an associated power spike is reduced or eliminated.

公开(公告)号：US12073108B2

公开(公告)日：2024-08-27

申请号：US17833718

申请日：2022-06-06

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Christopher G. Wieduwilt

IPC: G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/1668

Abstract: Apparatuses and methods can be related to placing memory in a computing system. The memory modules can be placed in memory slots to couple the memory modules to the computing system. The memory modules and/or the memory slots can have thermal qualities which can be utilized to determine which of the memory modules are placed on which of the memory slots.

公开(公告)号：US20240145341A1

公开(公告)日：2024-05-02

申请号：US18406636

申请日：2024-01-08

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Christopher G. Wieduwilt

IPC: H01L23/467 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L23/467 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/1094

Abstract: An improved memory module and methods for constructing the same are disclosed herein. The memory module includes a substrate having a first surface and a second surface opposite the first surface, each having a central portion, a first array area and a second array area. The first array area is cooler than the second array area during operation. The memory module also includes a power management integrated circuit attached to the central portion of the first surface. The memory module also includes a first semiconductor die attached to the substrate in the first array area. The first semiconductor die has a first performance rating of an operating parameter at high temperatures. The memory module also includes a second semiconductor die attached to the substrate in the second array area. The second semiconductor die has a second performance rating of an operating parameter better than the first performance rating at high temperatures.

公开(公告)号：US11881245B2

公开(公告)日：2024-01-23

申请号：US17939908

申请日：2022-09-07

Applicant: Micron Technology, Inc.

Inventor： Gary L. Howe ,  Miles S. Wiscombe ,  James S. Rehmeyer ,  Eric J. Stave

IPC: G11C11/4074 ,  G11C5/14 ,  G11C11/406 ,  G11C11/4076 ,  G11C5/04

CPC classification number: G11C11/406 ,  G11C5/04 ,  G11C11/4074 ,  G11C11/4076

Abstract: Methods, apparatuses, and systems related to voltage management of memory apparatuses/systems are described. The memory device can include circuitry configured to determine an operating frequency of a clock signal for an ongoing or an upcoming memory operation. The memory device may generate a control indicator for increasing a system voltage for higher operating frequencies, for decreasing the system voltage for lower operating frequencies, or a combination thereof.

公开(公告)号：US11676052B2

公开(公告)日：2023-06-13

申请号：US16849819

申请日：2020-04-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Debra M. Bell ,  James S. Rehmeyer ,  Brett K. Dodds ,  Anthony D. Veches ,  Libo Wang ,  Di Wu

IPC: G06N5/047 ,  G06N20/00 ,  H04L67/12 ,  H04L67/10 ,  H04L9/40 ,  G16Y10/75

CPC classification number: G06N5/047 ,  G06N20/00 ,  H04L63/1408 ,  H04L67/10 ,  H04L67/12 ,  G16Y10/75

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods for an internet of things (IoT) system to include edge devices that perform at least some functions without communicating with a cloud computing system. An edge device may include a memory with on-memory pattern matching capabilities. The edge device may perform pattern matching operations on data collected by the edge device or sensors in communication with the edge device. Based on results of the pattern matching operations, the edge device may perform various functions, such as transmitting data to the cloud computing system, activating an alarm, and/or changing a frequency at which data is transmitted.

公开(公告)号：US20230120654A1

公开(公告)日：2023-04-20

申请号：US18084135

申请日：2022-12-19

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis ,  James S. Rehmeyer ,  Baekkyu Choi ,  Yogesh Sharma ,  Eric J. Stave ,  Brian W. Huber ,  Miles S. Wiscombe

IPC: G11C11/406

Abstract: Methods, systems, and devices for voltage adjustment based on, for example, pending refresh operations are described. A memory device may periodically perform refresh operations to refresh volatile memory cells and may at times postpone performing one or more refresh operations. A memory device may determine a quantity of pending (e.g., postponed) refresh operations, such as by determining a quantity of refresh intervals that have elapsed without receiving or executing a refresh command, among other methods. A memory device may pre-emptively adjust (or cause to be adjusted) a supply voltage associated with the memory device or memory device component based on the quantity of pending refresh operations to prepare for the current demand associated with the performing the one or more pending refresh operations. For example, the memory device may increase a supply voltage associated with one or more components to prepare for performing multiple pending refresh operations.

公开(公告)号：US20230068666A1

公开(公告)日：2023-03-02

申请号：US17718200

申请日：2022-04-11

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Christopher G. Wieduwilt

IPC: G11C5/02 ,  G11C5/04 ,  G11C29/50

Abstract: Methods of optimizing the placement of memories in a memory device including a substrate and an electrical component, and associated devices and systems, are disclosed herein. A representative method includes first testing the memories to determine at least one parameter for each of the memories indicating an ability of the memory to process signals from the electrical component. The method can further include labeling each memory with a label based on the parameter, the labels including at least a first label and a second label. The first label can indicate that the memories with the first label are better able to process signals from the electrical component than the memories with the second label. The method can further include electrically coupling the memories to the substrate such that the memories with the second label are positioned closer to the electrical component than the memories with the first label.

公开(公告)号：US20230066587A1

公开(公告)日：2023-03-02

申请号：US17833718

申请日：2022-06-06

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Christopher G. Wieduwilt

IPC: G06F3/06

Abstract: Apparatuses and methods can be related to placing memory in a computing system. The memory modules can be placed in memory slots to couple the memory modules to the computing system. The memory modules and/or the memory slots can have thermal qualities which can be utilized to determine which of the memory modules are placed on which of the memory slots.