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公开(公告)号：US11281526B2
公开(公告)日：2022-03-22
申请号：US17008442
申请日：2020-08-31
Applicant: QUALCOMM Incorporated
Inventor： Alain Artieri , Deepti Vijayalakshmi Sriramagiri , Dexter Tamio Chun , Jungwon Suh
Abstract: Disclosed are techniques for generating a parity check matrix representing an error correcting code (ECC) for protecting a plurality of bits of a message. In an aspect, a method includes initializing a matrix M to store selected three-bit codes, selecting a first three-bit code from a set L of three-bit combinations of a number of bits n of the ECC that minimizes a sum of squared row weights of each row of the matrix M, comparing the first three-bit code with each of a plurality of error syndromes, and calculating, based on no comparison of the first three-bit code with each of the plurality of error syndromes, new error syndromes and storing the new error syndromes, wherein the new error syndromes are calculated by comparing the first three-bit code with each three-bit code in the matrix M, and storing the first three-bit code in the matrix M.
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公开(公告)号：US10922168B2
公开(公告)日：2021-02-16
申请号：US16503368
申请日：2019-07-03
Applicant: QUALCOMM Incorporated
Inventor： Jungwon Suh , Alain Artieri , Dexter Tamio Chun , Deepti Vijayalakshmi Sriramagiri
Abstract: Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.
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公开(公告)号：US10332582B2
公开(公告)日：2019-06-25
申请号：US15667618
申请日：2017-08-02
Applicant: QUALCOMM Incorporated
Inventor： Jungwon Suh , Yanru Li , Michael Hawjing Lo , Dexter Tamio Chun
IPC: G11C7/00 , G11C11/406 , G11C7/10
Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.
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84.发明授权公开(公告)号：US10222853B2
公开(公告)日：2019-03-05
申请号：US15448327
申请日：2017-03-02
Applicant: QUALCOMM Incorporated
Inventor： Jungwon Suh , Dexter Tamio Chun , Michael Hawjing Lo
IPC: G06F1/32 , G11C7/10 , G06F12/06 , G06F13/16 , G06F1/3234 , G06F13/42 , G06F1/3225
Abstract: Power saving techniques for memory systems are disclosed. In particular, exemplary aspects of the present disclosure contemplate taking advantage of patterns that may exist within memory elements and eliminating duplicative data transfers. Specifically, if data is repetitive, instead of sending the same data repeatedly, the data may be sent only a single time with instructions that cause the data to be replicated at a receiving end to restore the data to its original repeated state.
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公开(公告)号：US10185515B2
公开(公告)日：2019-01-22
申请号：US14016717
申请日：2013-09-03
Applicant: QUALCOMM Incorporated
Inventor： Hyunsuk Shin , Jung Pill Kim , Dexter Tamio Chun , Jungwon Suh
Abstract: An enhanced multi chip package (eMCP) is provided including a unified memory controller. The UMC is configured to manage different types of memory, such as NAND flash memory and DRAM on the eMCP. The UMC provides storage memory management, DRAM management, DRAM accessibility for storage memory management, and storage memory accessibility for DRAM management. The UMC also facilitates direct data copying from DRAM to storage memory and vice versa. The direct copying may be initiated by the UMC without interaction from a host, or may be initiated by a host.
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Patent Agency Ranking
公开(公告)号：US20180197594A1
公开(公告)日：2018-07-12
申请号：US15400507
申请日：2017-01-06
Applicant: QUALCOMM INCORPORATED
Inventor： Yanru Li , Dexter Chun , Jungwon Suh
IPC: G11C11/408 , G11C11/406 , G11C11/4091
CPC classification number: G11C11/408 , G11C8/12 , G11C11/406 , G11C11/40603 , G11C11/40618 , G11C11/4091
Abstract: Systems, methods, and computer programs are disclosed for providing coincident memory bank access. One embodiment is a memory device comprising a first bank, a second bank, a first bank resource, and a second bank resource. The first bank has a first set of bitlines for accessing a first set of rows in a first memory cell array. The second bank has a second set of bitlines for accessing a second set of rows in a second memory cell array. The first bank resource and the second bank resource are selectively connected to the first set of bitlines or the second set of bitlines via a cross-connect switch.
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公开(公告)号：US09965352B2
公开(公告)日：2018-05-08
申请号：US15151329
申请日：2016-05-10
Applicant: QUALCOMM Incorporated
Inventor： Jungwon Suh , David Ian West
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1048 , G11C29/52
Abstract: A memory device may include link error correction code (ECC) decoder and correction circuitry. The ECC decoder and correction circuitry may be arranged in a write path and configured for link error detection and correction of write data received over a data link. The memory device may also include memory ECC encoder circuitry. The memory ECC encoder circuitry may be arranged in the write path and configured for memory protection of the write data during storage in a memory array.
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公开(公告)号：US09779798B1
公开(公告)日：2017-10-03
申请号：US15400515
申请日：2017-01-06
Applicant: QUALCOMM INCORPORATED
Inventor： Yanru Li , Dexter Chun , Jungwon Suh , Alexander Gantman
IPC: G11C7/00 , G11C11/4078 , G11C11/406
CPC classification number: G11C8/12 , G11C7/1063 , G11C11/40603 , G11C11/40618 , G11C11/4087
Abstract: Systems, methods, and computer programs for providing row tamper protection in a multi-bank memory cell array. One method comprises monitoring row activation activity for each of a plurality of banks in a multi-bank memory cell array. In response to monitoring the row activation activity, a row activation counter table is stored in a memory. The row activation counter table comprises a plurality of row address entries, each row address entry having a corresponding row activation counter. In response to detecting one of the plurality of row activation counters has exceeded a threshold indicating suspicious row tampering, the corresponding row address entry associated with the row activation counter exceeding the threshold is determined. A refresh operation is performed on one or more rows adjacent to the row address having the row activation counter exceeding the threshold.
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公开(公告)号：US20170017587A1
公开(公告)日：2017-01-19
申请号：US15204755
申请日：2016-07-07
Applicant: QUALCOMM Incorporated
Inventor： David West , Vaishnav Srinivas , Michael Brunolli , Jungwon Suh
CPC classification number: G06F13/1689 , G06F13/4068 , G06F2213/0038 , G11C7/222 , H03L7/0807 , Y02D10/14 , Y02D10/151
Abstract: Methods, apparatus, and system for use in adaptive communication interfaces are disclosed. An adaptive communication interface is provided, in which a high-speed clock provided in a high-speed mode of operation is suppressed in a low-power mode of operation. In the low-power mode of operation, a low-speed command dock is used for data transfers between a memory device and a system-on-chip, applications processor or other device. A method for operating the adaptive communication interface may include using a first clock signal to control transmissions of commands to a memory device over a command bus. In a first mode of operation, the first clock signal controls data transmissions over the adaptive communication interface. In a second mode of operation, the second clock signal controls data transmissions over the adaptive communication interface. The frequency of the second clock signal may be greater than the frequency of the first clock signal.
Abstract translation: 公开了在自适应通信接口中使用的方法，装置和系统。 提供了一种自适应通信接口，其中在低功率操作模式中抑制了以高速操作模式提供的高速时钟。 在低功耗操作模式下，低速指令基座用于存储器件与片上系统，应用处理器或其他器件之间的数据传输。 用于操作自适应通信接口的方法可以包括使用第一时钟信号来通过命令总线控制对存储器设备的命令的传输。 在第一操作模式中，第一时钟信号控制通过自适应通信接口的数据传输。 在第二种操作模式中，第二时钟信号通过自适应通信接口控制数据传输。 第二时钟信号的频率可以大于第一时钟信号的频率。
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公开(公告)号：US09411727B2
公开(公告)日：2016-08-09
申请号：US14963201
申请日：2015-12-08
Applicant: QUALCOMM INCORPORATED
Inventor： Xiangyu Dong , Xiaochun Zhu , Jungwon Suh
CPC classification number: G06F12/0802 , G06F12/08 , G06F12/0855 , G06F12/0864 , G06F2212/1016 , G06F2212/22 , G06F2212/222 , G06F2212/60 , G11C7/1015 , G11C7/1039 , G11C7/1084 , G11C11/165 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/0002 , G11C2207/2245 , G11C2207/2272 , G11C2207/2281 , G11C2207/229
Abstract: A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes receiving a read command and executing the read command before executing a next write sub-command.
Abstract translation: 读取和写入电阻式存储器高速缓存的方法包括接收写入命令并将写入命令分成多个写入子命令。 该方法还包括在执行下一个写入子命令之前接收读取命令并执行读取命令。
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