公开(公告)号：US20140147941A1

公开(公告)日：2014-05-29

申请号：US14172208

申请日：2014-02-04

申请人： QUALCOMM Incorporated

发明人： Xia Li ,  Xiaochun Zhu ,  Seung Hyuk Kang

IPC分类号： H01L43/12

CPC分类号： H01L43/12 ,  B82Y10/00 ,  G11C11/161 ,  H01L27/228 ,  H01L43/08

摘要： A semiconductor device includes a magnetic tunnel junction (MTJ) storage element configured to be disposed in a common interlayer metal dielectric (IMD) layer with a logic element. Cap layers separate the common IMD layer from a top and bottom IMD layer. Top and bottom electrodes are coupled to the MTJ storage element. Metal connections to the electrodes are formed in the top and bottom IMD layers respectively through vias in the separating cap layers. Alternatively, the separating cap layers are recessed and the bottom electrodes are embedded, such that direct contact to metal connections in the bottom IMD layer is established. Metal connections to the top electrode in the common IMD layer are enabled by isolating the metal connections from the MTJ storage elements with metal islands and isolating caps.

摘要翻译： 半导体器件包括被配置为设置在具有逻辑元件的公共层间金属电介质（IMD）层中的磁隧道结（MTJ）存储元件。 盖层将公共IMD层与顶部和底部IMD层分开。 顶部和底部电极耦合到MTJ存储元件。 金属与电极的连接分别通过分离盖层中的通孔形成在顶部和底部IMD层中。 或者，分离盖层是凹进的并且底部电极被嵌入，从而建立与底部IMD层中的金属连接的直接接触。 通过用金属岛和隔离帽隔离与MTJ存储元件的金属连接来实现与公共IMD层中顶部电极的金属连接。

公开(公告)号：US20140038312A1

公开(公告)日：2014-02-06

申请号：US14048918

申请日：2013-10-08

申请人： QUALCOMM Incorporated

发明人： Kangho Lee ,  Xiaochun Zhu ,  Xia Li ,  Seung Hyuk Kang

IPC分类号： H01L43/02

CPC分类号： H01L43/02 ,  B82Y25/00 ,  B82Y40/00 ,  G06F17/5068 ,  H01F10/3254 ,  H01F10/329 ,  H01F41/309 ,  H01F41/32 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, a non-transitory computer-readable medium includes processor executable instructions. The instructions, when executed by a processor, cause the processor to initiate deposition of a capping material on a free layer of a magnetic tunneling junction structure to form a capping layer. The instructions, when executed by the processor, cause the processor to initiate oxidization of a first layer of the capping material to form a first oxidized layer of oxidized material.

摘要翻译： 公开了一种磁性隧道接合装置及其制造方法。 在特定实施例中，非暂时计算机可读介质包括处理器可执行指令。 当处理器执行时，指令使处理器开始在磁隧道结结构的自由层上沉积封盖材料以形成覆盖层。 所述指令在由所述处理器执行时使所述处理器启动所述封盖材料的第一层的氧化以形成氧化材料的第一氧化层。

公开(公告)号：US11290109B1

公开(公告)日：2022-03-29

申请号：US17030087

申请日：2020-09-23

申请人： QUALCOMM Incorporated

发明人： Foua Vang ,  Hyeokjin Lim ,  Seung Hyuk Kang ,  Venugopal Boynapalli ,  Shitiz Arora

IPC分类号： H01L21/00 ,  H03K19/094 ,  H01L23/528

摘要： A MOS IC includes a MOS logic cell that includes first and second sets of transistor logic in first and second subcells, respectively. The first and second sets of transistor logic are functionally isolated from each other. The MOS logic cell includes a first set of Mx layer interconnects on an Mx layer extending in a first direction over the first and second subcells. A first subset of the first set of Mx layer interconnects is coupled to inputs/outputs of the first set of transistor logic in the first subcell and is unconnected to the second set of transistor logic. Each of the first subset of the first set of Mx layer interconnects extends from the corresponding input/output of the first set of transistor logic of the first subcell to the second subcell, and is the corresponding input/output of the first set of transistor logic.

公开(公告)号：US11237580B1

公开(公告)日：2022-02-01

申请号：US17015486

申请日：2020-09-09

申请人： QUALCOMM Incorporated

发明人： Giby Samson ,  Foua Vang ,  Ramaprasath Vilangudipitchai ,  Seung Hyuk Kang ,  Venugopal Boynapalli

IPC分类号： G05F1/46 ,  H03K19/00 ,  H03K17/22

摘要： A system includes: a first power supply; a second power supply; a headswitch disposed between the first power supply and logic circuitry; an enable driver coupling the second power supply to a control terminal of the headswitch; and a voltage generator operable to adjust a control voltage from the second power supply to the control terminal of the headswitch in response to a first voltage level of the first power supply exceeding a reference voltage level.

公开(公告)号：US10833254B2

公开(公告)日：2020-11-10

申请号：US16431490

申请日：2019-06-04

申请人： QUALCOMM Incorporated

发明人： Chando Park ,  Jimmy Jianan Kan ,  Peiyuan Wang ,  Seung Hyuk Kang

IPC分类号： H01L43/06 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16 ,  H01L43/08 ,  H01F10/32

摘要： A perpendicular magnetic tunnel junction may include a free layer, a reference layer, and a barrier layer. The barrier layer may be arranged between the free layer and the reference layer. The barrier layer may include a first interface and a second interface. The first interface may face the free layer, and a second interface may face the reference layer. The first interface may not physically correlate with the second interface.

公开(公告)号：US10740017B2

公开(公告)日：2020-08-11

申请号：US15963668

申请日：2018-04-26

申请人： QUALCOMM Incorporated

发明人： Chando Park ,  Wei-Chuan Chen ,  Sungryul Kim ,  Adam Edward Newham ,  Seung Hyuk Kang ,  Rashid Ahmed Akbar Attar

IPC分类号： G06F3/06 ,  G11C11/00 ,  G11C29/52 ,  A61N1/372 ,  H04W4/80

摘要： Aspects of the present disclosure relate to protecting the contents of memory in an electronic device, and in particular to systems and methods for transferring data between memories of an electronic device in the presence of strong magnetic fields. In one embodiment, a method of protecting data in a memory in an electronic device includes storing data in a first memory in the electronic device; determining, via a magnetic sensor, a strength of an ambient magnetic field; comparing the strength of the ambient magnetic field to a threshold; transferring the data in the first memory to a second memory in the electronic device upon determining that the strength of the ambient magnetic field exceeds the threshold; and transferring the data from the second memory to the first memory upon determining that the strength of the ambient magnetic field no longer exceeds the threshold.

公开(公告)号：US20200066968A1

公开(公告)日：2020-02-27

申请号：US16107484

申请日：2018-08-21

申请人： QUALCOMM Incorporated

发明人： Chando Park ,  Sungryul Kim ,  Seung Hyuk Kang

IPC分类号： H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01F10/32 ,  G11C11/16 ,  H01L27/22

摘要： Aspects disclosed include spin-orbit torque (SOT) magnetic tunnel junction (MTJ) (SOT-MTJ) devices employing perpendicular and in-plane free layer magnetic anisotropy to facilitate perpendicular magnetic orientation switching. A free layer in a MTJ in the SOT-MTJ device includes both a perpendicular magnetic anisotropy (PMA) region(s) and an in-plane magnetic anisotropy (IMA) region(s). A spin torque is generated in the free layer when a SOT switching current flows through an electrode adjacent to the free layer sufficient to switch the magnetic moment of the free layer to an in-plane magnetic orientation. To prevent a non-deterministic perpendicular magnetic orientation after the SOT switching current is removed, the free layer also includes the IMA region(s) to provide an in-plane magnetization to generate an effective magnetic field in the free layer to assist in switching the magnetic moment of the free layer past an in-plane magnetic orientation to a perpendicular magnetic orientation.

公开(公告)号：US10483457B1

公开(公告)日：2019-11-19

申请号：US16102941

申请日：2018-08-14

申请人： QUALCOMM Incorporated

发明人： Hochul Lee ,  Chando Park ,  Seung Hyuk Kang

IPC分类号： H01L43/04 ,  H01L27/22 ,  H01L43/06 ,  G11C11/56 ,  G11C11/18 ,  G11C11/16

摘要： Aspects of the disclosure provide magnetoresistive random access memory (MRAM) and methods. The MRAM generally includes a first magnetic tunnel junction (MTJ) storage element comprising a first fixed layer, a first insulating layer, and a first free layer, and a second MTJ storage element comprising a second fixed layer, a second insulating layer, and a second free layer. The MRAM further includes a conductive layer connected to a source line, first bit line, and a second bit line, wherein the first MTJ storage element is disposed above and connected to the conductive layer and the first bit line at a first end and connected to the first bit line at a second end, and wherein the second MTJ storage element is disposed above and connected to the conductive layer and the second bit line at a first end and connected to the second bit line at a second end.

公开(公告)号：US20190342106A1

公开(公告)日：2019-11-07

申请号：US15969043

申请日：2018-05-02

申请人： QUALCOMM Incorporated

发明人： Xia Li ,  Seung Hyuk Kang ,  Nicholas Ka Ming Stevens-Yu

IPC分类号： H04L9/32 ,  G11C11/419 ,  G11C11/418 ,  G06F21/75

摘要： Physically unclonable function (PUF) circuits employing multiple PUF memories to decouple a PUF challenge input from a PUF response output for enhanced security. The PUF circuit includes a PUF challenge memory and a PUF response memory. In response to a read operation, the PUF challenge memory uses a received PUF challenge input data word to address PUF challenge memory arrays therein to generate a plurality of intermediate PUF challenge output data words. The PUF response memory is configured to generate a second, final PUF response output data word in response to intermediate PUF challenge output data words. In this manner, it is more difficult to learn the challenge-response behavior of the PUF circuit, because the PUF challenge input data word does not directly address a memory array that stores memory states representing final logic values in the PUF response output data word.

公开(公告)号：US10460780B2

公开(公告)日：2019-10-29

申请号：US15939923

申请日：2018-03-29

申请人： QUALCOMM Incorporated

发明人： Sungryul Kim ,  Chando Park ,  Seung Hyuk Kang

IPC分类号： G11C11/16 ,  H04L9/32 ,  H01L43/08 ,  H01L27/22

摘要： Magneto-resistive random access memory (MRAM) employing an integrated physically unclonable function (PUF) memory. The MRAM includes an MRAM array comprising an MRAM data array of data MRAM bit cells and an MRAM PUF array comprising PUF MRAM bit cells to form an integrated MRAM PUF array in the MRAM array. A resistance sensed from the PUF MRAM bit cells is compared to a reference resistance between the reference MRAM bit cells in the accessed MRAM bit cell row circuit in response to a read operation to cancel or mitigate the effect of process variations on MRAM bit cell resistance. The difference in sensed resistance and reference resistance is used to generate a random PUF output. By integrating the MRAM PUF array into an MRAM array containing an MRAM data array, access circuitry can be shared to control access to the MRAM data array and MRAM PUF, thus saving memory area.