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    High-efficiency DC/DC voltage converter including capacitive switching pre-converter and down inductive switching post-regulator
    81.
    发明申请
    High-efficiency DC/DC voltage converter including capacitive switching pre-converter and down inductive switching post-regulator 有权
    高效率直流/直流电压转换器包括电容式开关转换器和降压感应开关后稳压器

    公开(公告)号：US20090059630A1

    公开(公告)日：2009-03-05

    申请号：US11890994

    申请日：2007-08-08

    申请人： Richard K. Williams

    发明人： Richard K. Williams

    IPC分类号： H02M3/139

    CPC分类号： H02M3/155 ,  H02M3/07 ,  H02M3/1588 ,  H02M2001/007 ,  Y02B70/1466

    摘要： A DC/DC converter includes a pre-converter stage, which may include a charge pump, and a post-regulator stage, which may include a Buck converter. The duty factor of the post-regulator stage is controlled by a feedback path that extends from the output terminal of the DC/DC converter to an input terminal in the post-regulator stage. The pre-converter steps the input DC voltage up or down by a positive or negative integral or fractional value, and the post-regulator steps the voltage down by a variable amount depending on the duty factor at which the post-regulator is driven. The converter overcomes the problems of noise glitches, poor regulation, and instability, even near unity input-to-output voltage conversion ratios.

    摘要翻译： DC / DC转换器包括可以包括电荷泵的预转换器级和可以包括降压转换器的后稳压器级。 后稳压器级的占空因数由在DC / DC转换器的输出端子延伸到后稳压器级中的输入端子的反馈路径控制。 预转换器将输入直流电压向上或向下递增正或负整数或分数值，并且后稳压器根据后调节器驱动的占空因数将电压降低可变量。 该转换器克服了噪声毛刺的问题，调节不良和不稳定性，甚至接近一致的输入/输出电压转换比。

    Method of fabricating trench-constrained isolation diffusion for semiconductor devices
    85.
    发明申请
    Method of fabricating trench-constrained isolation diffusion for semiconductor devices 有权
    制造用于半导体器件的沟槽约束隔离扩散的方法

    公开(公告)号：US20080293214A1

    公开(公告)日：2008-11-27

    申请号：US12221155

    申请日：2008-07-31

    申请人： Richard K. Williams ,  Michael E. Cornell ,  Wai Tien Chan

    发明人： Richard K. Williams ,  Michael E. Cornell ,  Wai Tien Chan

    IPC分类号： H01L21/762

    CPC分类号： H01L27/0826 ,  H01L21/8224 ,  H01L21/82285 ,  H01L27/0821 ,  H01L29/6625 ,  H01L29/66272 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped region diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer is formed at an interface between an epitaxial layer and a substrate, at a location generally below the dopant in the mesa. When the substrate is subjected to thermal processing, the buried layer diffuses upward, the dopant in the mesa diffuses downward until the two dopants merge to form an isolation region or a sinker extending downward from the surface of the epitaxial layer to the buried layer. In another embodiment, dopant is implanted between dielectrically filled trenches at a high energy up to several MeV, then diffused, combining the benefits of deep implantation and trenched constrained diffusion to achive deep diffusions with a minimal thermal budget.

    摘要翻译： 半导体衬底包括填充有电介质材料的一对沟槽。 引入到沟槽之间的台面中的掺杂剂被限制为当衬底经受热处理时横向扩散。 因此，半导体器件可以在衬底上更紧密地间隔开，并且可以增加器件的封装密度。 另外，沟槽约束掺杂区域比无约束扩散更快更深地扩散，从而减少完成所需深度扩散所需的时间和温度。 该技术可以用于诸如双极晶体管的半导体器件以及将器件彼此电隔离的隔离区域。 在一组实施例中，在外延层和衬底之间的界面处，在台面的通常低于掺杂剂的位置处形成掩埋层。 当衬底经受热处理时，掩埋层向上扩散，台面中的掺杂剂向下扩散直到两个掺杂剂合并形成从外延层的表面向掩埋层向下延伸的隔离区域或沉降片。 在另一个实施例中，掺杂剂以高达几MeV的高能量注入电介质填充的沟槽之间，然后扩散，将深度注入和沟槽约束扩散的优点结合起来，以最小的热预算进行深度扩散。

    Trench-constrained isolation diffusion for integrated circuit die
    86.
    发明申请
    Trench-constrained isolation diffusion for integrated circuit die 有权
    用于集成电路管芯的沟槽限制隔离扩散

    公开(公告)号：US20080290452A1

    公开(公告)日：2008-11-27

    申请号：US12221105

    申请日：2008-07-31

    申请人： Richard K. Williams ,  Michael E. Cornell ,  Wai Tien Chan

    发明人： Richard K. Williams ,  Michael E. Cornell ,  Wai Tien Chan

    IPC分类号： H01L29/00

    CPC分类号： H01L27/0826 ,  H01L21/8224 ,  H01L21/82285 ,  H01L27/0821 ,  H01L29/6625 ,  H01L29/66272 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped region diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer is formed at an interface between an epitaxial layer and a substrate, at a location generally below the dopant in the mesa. When the substrate is subjected to thermal processing, the buried layer diffuses upward, the dopant in the mesa diffuses downward until the two dopants merge to form an isolation region or a sinker extending downward from the surface of the epitaxial layer to the buried layer. In another embodiment, dopant is implanted between dielectrically filled trenches at a high energy up to several MeV, then diffused, combining the benefits of deep implantation and trenched constrained diffusion to achieve deep diffusions with a minimal thermal budget.

    摘要翻译： 半导体衬底包括填充有电介质材料的一对沟槽。 引入到沟槽之间的台面中的掺杂剂被限制为当衬底经受热处理时横向扩散。 因此，半导体器件可以在衬底上更紧密地间隔开，并且可以增加器件的封装密度。 另外，沟槽约束掺杂区域比无约束扩散更快更深地扩散，从而减少完成所需深度扩散所需的时间和温度。 该技术可以用于诸如双极晶体管的半导体器件以及将器件彼此电隔离的隔离区域。 在一组实施例中，在外延层和衬底之间的界面处，在台面的通常低于掺杂剂的位置处形成掩埋层。 当衬底经受热处理时，掩埋层向上扩散，台面中的掺杂剂向下扩散直到两个掺杂剂合并形成从外延层的表面向掩埋层向下延伸的隔离区域或沉降片。 在另一个实施方案中，掺杂剂以高达几MeV的高能量注入电介质填充的沟槽之间，然后扩散，结合深度注入和沟槽约束扩散的优点，以最小的热预算实现深扩散。

    Lateral MOSFET
    90.
    发明申请
    Lateral MOSFET 有权
    横向MOSFET

    公开(公告)号：US20080237706A1

    公开(公告)日：2008-10-02

    申请号：US12002437

    申请日：2007-12-17

    申请人： Richard K. Williams ,  Donald Ray Disney ,  Wai Tien Chan

    发明人： Richard K. Williams ,  Donald Ray Disney ,  Wai Tien Chan

    IPC分类号： H01L29/78

    CPC分类号： H01L29/735 ,  H01L21/761 ,  H01L21/82285 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826 ,  H01L27/092 ,  H01L29/7322 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A lateral MOSFET formed in a substrate of a first conductivity type includes a gate formed atop a gate dielectric layer over a surface of the substrate, a drain region of a second conductivity type, a source region of a second conductivity type, and a body region of the first conductivity type which extends under the gate. The body region may have a non-monotonic vertical doping profile with a portion located deeper in the substrate having a higher doping concentration than a portion located shallower in the substrate. The lateral MOSFET may be drain-centric, with the source region and an optional dielectric-filled trench surrounding the drain region.

    摘要翻译： 形成在第一导电类型的衬底中的横向MOSFET包括形成在衬底的表面上的栅极电介质层顶部的栅极，第二导电类型的漏极区域，第二导电类型的源极区域和主体区域 的第一导电类型在栅极下延伸。 体区域可以具有非单调垂直掺杂分布，其中位于衬底中的部分位于比衬底中较浅的部分具有更高的掺杂浓度的部分。 横向MOSFET可以以漏极为中心，源极区域和围绕漏极区域的可选的介电填充沟槽。