利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

117 条记录 (耗时 0.023 秒)

    Via first plus via last technique for IC interconnects
    82.
    发明授权
    Via first plus via last technique for IC interconnects 有权
    通过第一个加上通过IC互连的最后技术

    公开(公告)号：US07939926B2

    公开(公告)日：2011-05-10

    申请号：US12334433

    申请日：2008-12-12

    申请人： Kenneth Kaskoun ,  Shiqun Gu ,  Bart Swinnen

    发明人： Kenneth Kaskoun ,  Shiqun Gu ,  Bart Swinnen

    IPC分类号： H01L23/02

    CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2224/06181 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are coupled together. The first set of vias are physically smaller than the second set of vias. The first set of vias are produced prior to circuitry on the die, and the second set of vias are produced after circuitry on the die. A second die having a set of interconnects is stacked relative to the first die in which the interconnects couple to the first set of vias.

    摘要翻译： 多层IC器件包含第一裸片，其包括具有第一组和第二组通孔的衬底。 第一组通孔从衬底的一侧延伸，并且第二组通孔从衬底的相对侧延伸。 两组通孔耦合在一起。 第一组通孔在物理上小于第二组通孔。 第一组通孔在芯片上的电路之前产生，并且第二组通孔在芯片上的电路之后产生。 具有一组互连件的第二管芯相对于第一管芯堆叠，其中互连件耦合到第一组通孔。

    Interconnect Sensor for Detecting Delamination
    83.
    发明申请
    Interconnect Sensor for Detecting Delamination 失效
    用于检测分层的互连传感器

    公开(公告)号：US20110101347A1

    公开(公告)日：2011-05-05

    申请号：US12613444

    申请日：2009-11-05

    申请人： Brian Matthew Henderson ,  Shiqun Gu ,  Homyar C. Mogul ,  Mark M. Nakamoto ,  Arvind Chandrasekaran

    发明人： Brian Matthew Henderson ,  Shiqun Gu ,  Homyar C. Mogul ,  Mark M. Nakamoto ,  Arvind Chandrasekaran

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L22/34 ,  G01N3/066 ,  G01N2203/0096

    摘要： An interconnect sensor for detecting delamination due to coefficient of thermal expansion mismatch and/or mechanical stress. The sensor comprises a conductive path that includes a via disposed between two back end of line metal layers separated by a dielectric. The via is coupled between a first probe structure and a second probe structure and mechanically coupled to a stress inducing structure. The via is configured to alter the conductive path in response to mechanical stress caused by the stress inducing structure. The stress inducing structure can be a through silicon via or a solder ball. The dielectric material can be a low-k dielectric material. In another embodiment, a method of forming an interconnect sensor is provided for detecting delamination.

    摘要翻译： 用于检测由于热膨胀失配系数和/或机械应力引起的分层的互连传感器。 该传感器包括导电路径，该导电路径包括通过电介质隔开的线金属层的两个后端之间的通孔。 通孔耦合在第一探针结构和第二探针结构之间，并机械耦合到应力诱导结构。 通孔配置成响应于由应力诱导结构引起的机械应力而改变导电路径。 应力诱导结构可以是硅通孔或焊球。 介电材料可以是低k电介质材料。 在另一个实施例中，提供形成互连传感器的方法用于检测分层。

    Self-aligned cell integration scheme
    84.
    发明授权
    Self-aligned cell integration scheme 失效
    自对准单元集成方案

    公开(公告)号：US07915122B2

    公开(公告)日：2011-03-29

    申请号：US11312849

    申请日：2005-12-20

    申请人： Richard J. Carter ,  Hemanshu D. Bhatt ,  Shiqun Gu ,  Peter A. Burke ,  James R. B. Elmer ,  Sey-Shing Sun ,  Byung-Sung Kwak ,  Verne Hornback

    发明人： Richard J. Carter ,  Hemanshu D. Bhatt ,  Shiqun Gu ,  Peter A. Burke ,  James R. B. Elmer ,  Sey-Shing Sun ,  Byung-Sung Kwak ,  Verne Hornback

    IPC分类号： H01L21/336

    CPC分类号： H01L51/0018 ,  B82Y10/00 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0545 ,  Y10S977/742

    摘要： A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.

    摘要翻译： 一种形成自对准逻辑单元的方法。 在底部电极上形成纳米管层。 在纳米管层上形成夹层。 夹层覆盖纳米管层，从而保护纳米管层。 在钳位层上形成电介质层。 蚀刻介电层。 钳位层提供蚀刻停止并保护纳米管层。 用各向同性蚀刻剂蚀刻钳夹层，蚀刻介质层下方的夹层，产生电介质层的重叠，并引起钳位层和电介质层之间的自对准。 在纳米管层上形成间隔层。 除了围绕电介质层的边缘的环形部分之外，蚀刻间隔层。 除了夹持层，电介质层和间隔层中的至少一个的部分以外，蚀刻纳米管层，从而导致夹紧层之间的自对准，与电介质层的重叠，间隔层， 和纳米管层。

    Techniques for precision pattern transfer of carbon nanotubes from photo mask to wafers
    85.
    发明授权
    Techniques for precision pattern transfer of carbon nanotubes from photo mask to wafers 失效
    碳纳米管从光掩模到晶圆的精密图案转移的技术

    公开(公告)号：US07911034B2

    公开(公告)日：2011-03-22

    申请号：US12471175

    申请日：2009-05-22

    申请人： Shiqun Gu ,  Peter G. McGrath ,  James Elmer ,  Richard J. Carter ,  Thomas Rueckes

    发明人： Shiqun Gu ,  Peter G. McGrath ,  James Elmer ,  Richard J. Carter ,  Thomas Rueckes

    IPC分类号： H01L29/12

    CPC分类号： H01L21/76838 ,  B82Y10/00 ,  H01L21/32136 ,  H01L21/32139 ,  H01L51/0018 ,  H01L51/0048 ,  Y10S977/742

    摘要： A method for patterning CNTs on a wafer wherein a CNT layer is provided on a substrate, a hard mask film is deposited on the CNT layer, a BARC layer (optional) is coated on the hard mask film, and a resist is patterned on the BARC layer (or directly on the hard mask film if the BARC layer is not included). Then, the resist pattern is effectively transferred to the hard mask film by etching the BARC layer (if provided) and etching partly into, but not entirely through, the hard mask film (i.e., etching is stopped before reaching the CNT layer). Then, the resist and the BARC layer (if provided) is stripped, and the hard mask pattern is effectively transferred to the CNTs by etching away (preferably by using C1, F plasma) the portions of the hard mask which have been already partially etched away.

    摘要翻译： 一种用于在晶片上图案化CNT的方法，其中CNT层设置在基板上，硬掩模膜沉积在CNT层上，BARC层（可选）涂覆在硬掩模膜上，并且抗蚀剂在 BARC层（或直接在硬掩模膜上，如果不包括BARC层）。 然后，通过蚀刻BARC层（如果提供）并且部分地蚀刻到硬掩模膜上（而不是完全通过）硬掩模膜（即，在到达CNT层之前停止蚀刻），将抗蚀剂图案有效地转移到硬掩模膜。 然后，剥离抗蚀剂和BARC层（如果提供的话），并且通过蚀刻掉（优选使用C1，F等离子体）将硬掩模图案有效地转移到CNT上，硬掩模的已经被部分蚀刻的部分 远。

    Low Cost Die-To-Wafer Alignment/Bond For 3d IC Stacking
    87.
    发明申请
    Low Cost Die-To-Wafer Alignment/Bond For 3d IC Stacking 有权
    低成本芯片对晶片对齐/贴合3d IC堆叠

    公开(公告)号：US20100075460A1

    公开(公告)日：2010-03-25

    申请号：US12236967

    申请日：2008-09-24

    申请人： Shiqun Gu ,  Thomas R. Toms

    发明人： Shiqun Gu ,  Thomas R. Toms

    IPC分类号： H01L21/00

    CPC分类号： H01L23/544 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54406 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2223/5448 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00

    摘要： The cost associated with alignment in a stacked IC device can be reduced by aligning multiple die instead of a single die during the alignment step. In one embodiment, the alignment structures are placed in the scribe line instead of within the die itself. Aligning four die instead of one eliminates the need for as many alignment indicators and thus more silicon on the wafer can be used for active areas. In addition, this method allows for yield improvement through binning of dies having the same yield configuration.

    摘要翻译： 在对准步骤期间，可以通过对准多个管芯而不是单个管芯来降低与叠置的IC器件中的对准相关的成本。 在一个实施例中，对准结构被放置在划线中，而不是在模具本身内。 对准四个模具而不是一个消除了对于多个对准指示器的需要，因此在晶片上更多的硅可用于有源区域。 此外，该方法允许通过对具有相同产量构型的模具进行分级来提高产量。

    Capacitive MEMS-Based Display with Touch Position Sensing
    88.
    发明申请
    Capacitive MEMS-Based Display with Touch Position Sensing 审中-公开
    具有触摸位置检测功能的电容式MEMS基显示器

    公开(公告)号：US20100045630A1

    公开(公告)日：2010-02-25

    申请号：US12194412

    申请日：2008-08-19

    申请人： Shiqun Gu ,  Matthew Nowak

    发明人： Shiqun Gu ,  Matthew Nowak

    IPC分类号： G06F3/045

    CPC分类号： G06F3/0412 ,  G06F3/044

    摘要： A micro-electro-mechanical systems (MEMS) pixel for display and touch position sensing includes a substrate and a capacitive element. The capacitive element includes one or more pixels having a first conductive platelet above the substrate, and a second conductive platelet above and spaced apart from the first conductive platelet, the two platelets forming the capacitive element. A connection to each platelet provides for applying a voltage, wherein the platelet separation changes according to the applied voltage. A transparent dielectric plate, spaced apart from and positioned opposite the substrate, covers the at least one pixel. A capacitance sensing circuit attached to the connection to each platelet of the pixel senses changes in capacitance not resulting from the applied voltage.

    摘要翻译： 用于显示和触摸位置感测的微电子机械系统（MEMS）像素包括基板和电容元件。 电容元件包括一个或多个像素，其具有在衬底上方的第一导电片，以及在第一导电片上方并与第一导电片形成间隔开的第二导电片，所述两片片形成电容元件。 与每个血小板的连接提供施加电压，其中血小板分离根据所施加的电压而改变。 与衬底间隔开并与衬底相对设置的透明电介质板覆盖至少一个像素。 附接到与像素的每个血小板的连接的电容感测电路感测不是由施加电压引起的电容变化。

    Predictive Modeling of Interconnect Modules for Advanced On-Chip Interconnect Technology
    89.
    发明申请
    Predictive Modeling of Interconnect Modules for Advanced On-Chip Interconnect Technology 失效
    用于高级片上互连技术的互连模块的预测建模

    公开(公告)号：US20090327983A1

    公开(公告)日：2009-12-31

    申请号：US12474297

    申请日：2009-05-29

    申请人： Xia Li ,  Wei Zhao ,  Yu Cao ,  Shiqun Gu ,  Seung H. Kang ,  Matthew Nowak

    发明人： Xia Li ,  Wei Zhao ,  Yu Cao ,  Shiqun Gu ,  Seung H. Kang ,  Matthew Nowak

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A computer program product estimates performance of an interconnect structure of a semiconductor integrated circuit (IC). The program product includes code executing on a computer to calculate at least one electrical characteristic of the interconnect structure based on input data accounting for multiple layers of the interconnect structure. The electrical characteristics can be capacitance, resistance, and/or inductance. The capacitance may be based upon multiple components, including a fringe capacitance component, a terminal capacitance component, and a coupling capacitance component.

    摘要翻译： 计算机程序产品估计半导体集成电路（IC）的互连结构的性能。 程序产品包括在计算机上执行的代码，用于基于考虑到互连结构的多层的输入数据来计算互连结构的至少一个电特性。 电气特性可以是电容，电阻和/或电感。 电容可以基于多个分量，包括边缘电容分量，端子电容分量和耦合电容分量。

    Method and apparatus for reducing microtrenching for borderless vias created in a dual damascene process
    90.
    发明授权
    Method and apparatus for reducing microtrenching for borderless vias created in a dual damascene process 有权
    用于减少在双镶嵌工艺中产生的无边界通孔的微切削的方法和装置

    公开(公告)号：US06794304B1

    公开(公告)日：2004-09-21

    申请号：US10631528

    申请日：2003-07-31

    申请人： Shiqun Gu ,  Masaichi Eda ,  Peter McGrath ,  Hong Lin ,  Jim Elmer

    发明人： Shiqun Gu ,  Masaichi Eda ,  Peter McGrath ,  Hong Lin ,  Jim Elmer

    IPC分类号： H01L21302

    CPC分类号： H01L21/76897 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76834

    摘要： A method of making a semiconductor device includes providing a first element formed of a first substantially electrically conductive material and having an upper surface. A second element adjacent to the first element is provided. The second element is formed of a first substantially non-electrically conductive material. An upper surface of the second element slopes downwardly toward the upper surface of the first element. A first layer of a second substantially non-electrically conductive material is disposed over the upper surface of the first element and the upper surface of the second element. The first layer has a thickness in the vertical direction that is greater in an area over the downward slope of the second element than in an area over the first element. An etching process is performed such that the layer is perforated above the upper surface of the first element and imperforated in the vertically thicker area above the downwardly sloping upper surface of the second element.

    摘要翻译： 制造半导体器件的方法包括提供由第一基本上导电的材料形成并具有上表面的第一元件。 提供了与第一元件相邻的第二元件。 第二元件由第一基本上不导电的材料形成。 第二元件的上表面朝向第一元件的上表面向下倾斜。 第二基本上非导电材料的第一层设置在第一元件的上表面和第二元件的上表面之上。 第一层具有在垂直方向上的厚度，该厚度在第二元件的向下倾斜度上比在第一元件上的区域中大得多。 进行蚀刻处理，使得该层在第一元件的上表面上方穿孔，并且在第二元件的向下倾斜的上表面上方的垂直较厚的区域中无孔。