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公开(公告)号:US08618539B2
公开(公告)日:2013-12-31
申请号:US12613444
申请日:2009-11-05
申请人: Brian Matthew Henderson , Shiqun Gu , Homyar C. Mogul , Mark M. Nakamoto , Arvind Chandrasekaran
发明人: Brian Matthew Henderson , Shiqun Gu , Homyar C. Mogul , Mark M. Nakamoto , Arvind Chandrasekaran
IPC分类号: H01L23/48
CPC分类号: H01L22/34 , G01N3/066 , G01N2203/0096
摘要: An interconnect sensor for detecting delamination due to coefficient of thermal expansion mismatch and/or mechanical stress. The sensor comprises a conductive path that includes a via disposed between two back end of line metal layers separated by a dielectric. The via is coupled between a first probe structure and a second probe structure and mechanically coupled to a stress inducing structure. The via is configured to alter the conductive path in response to mechanical stress caused by the stress inducing structure. The stress inducing structure can be a through silicon via or a solder ball. The dielectric material can be a low-k dielectric material. In another embodiment, a method of forming an interconnect sensor is provided for detecting delamination.
摘要翻译: 用于检测由于热膨胀失配系数和/或机械应力引起的分层的互连传感器。 该传感器包括导电路径,该导电路径包括通过电介质隔开的线金属层的两个后端之间的通孔。 通孔耦合在第一探针结构和第二探针结构之间,并机械耦合到应力诱导结构。 通孔配置成响应于由应力诱导结构引起的机械应力而改变导电路径。 应力诱导结构可以是硅通孔或焊球。 介电材料可以是低k电介质材料。 在另一个实施例中,提供形成互连传感器的方法用于检测分层。
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公开(公告)号:US20110101347A1
公开(公告)日:2011-05-05
申请号:US12613444
申请日:2009-11-05
申请人: Brian Matthew Henderson , Shiqun Gu , Homyar C. Mogul , Mark M. Nakamoto , Arvind Chandrasekaran
发明人: Brian Matthew Henderson , Shiqun Gu , Homyar C. Mogul , Mark M. Nakamoto , Arvind Chandrasekaran
IPC分类号: H01L23/48 , H01L21/768
CPC分类号: H01L22/34 , G01N3/066 , G01N2203/0096
摘要: An interconnect sensor for detecting delamination due to coefficient of thermal expansion mismatch and/or mechanical stress. The sensor comprises a conductive path that includes a via disposed between two back end of line metal layers separated by a dielectric. The via is coupled between a first probe structure and a second probe structure and mechanically coupled to a stress inducing structure. The via is configured to alter the conductive path in response to mechanical stress caused by the stress inducing structure. The stress inducing structure can be a through silicon via or a solder ball. The dielectric material can be a low-k dielectric material. In another embodiment, a method of forming an interconnect sensor is provided for detecting delamination.
摘要翻译: 用于检测由于热膨胀失配系数和/或机械应力引起的分层的互连传感器。 该传感器包括导电路径,该导电路径包括通过电介质隔开的线金属层的两个后端之间的通孔。 通孔耦合在第一探针结构和第二探针结构之间,并机械耦合到应力诱导结构。 通孔配置成响应于由应力诱导结构引起的机械应力而改变导电路径。 应力诱导结构可以是硅通孔或焊球。 介电材料可以是低k电介质材料。 在另一个实施例中,提供形成互连传感器的方法用于检测分层。
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公开(公告)号:US20110193212A1
公开(公告)日:2011-08-11
申请号:US12701642
申请日:2010-02-08
申请人: Shiqun Gu , Matthew Michael Nowak , Durodami J. Lisk , Thomas R. Toms , Urmi Ray , Jungwon Suh , Arvind Chandrasekaran
发明人: Shiqun Gu , Matthew Michael Nowak , Durodami J. Lisk , Thomas R. Toms , Urmi Ray , Jungwon Suh , Arvind Chandrasekaran
IPC分类号: H01L23/522 , H01L21/768
CPC分类号: H01L23/5286 , H01L23/3677 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/48 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05093 , H01L2224/13009 , H01L2224/13025 , H01L2224/13028 , H01L2224/131 , H01L2224/14505 , H01L2224/16145 , H01L2224/16146 , H01L2224/17517 , H01L2224/48091 , H01L2224/48227 , H01L2224/81136 , H01L2224/81193 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2225/06562 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: A semiconductor chip includes an array of electrical contacts and multiple vias coupling at least one circuit in the semiconductor chip to the array of electrical contacts. A first one of the electrical contacts of the array of electrical contacts is coupled to N vias, and a second one of the electrical contacts of the array of electrical contacts is coupled to M vias. M and N are positive integers of different values.
摘要翻译: 半导体芯片包括电连接阵列和将半导体芯片中的至少一个电路耦合到电接触阵列的多个通孔。 电触点阵列的电触点中的第一个耦合到N个通孔,并且电触点阵列的电触点中的第二个耦合到M个通孔。 M和N是不同值的正整数。
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公开(公告)号:US08482125B2
公开(公告)日:2013-07-09
申请号:US12837717
申请日:2010-07-16
IPC分类号: H01L23/488
CPC分类号: H01L24/81 , H01L21/76877 , H01L23/49816 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/742 , H01L25/0657 , H01L25/50 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/0347 , H01L2224/0361 , H01L2224/0401 , H01L2224/051 , H01L2224/05567 , H01L2224/056 , H01L2224/1145 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11472 , H01L2224/1161 , H01L2224/11849 , H01L2224/119 , H01L2224/13017 , H01L2224/13018 , H01L2224/13021 , H01L2224/13023 , H01L2224/13076 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/16058 , H01L2224/16148 , H01L2224/81193 , H01L2224/81203 , H01L2224/81815 , H01L2225/06513 , H01L2924/00013 , H01L2924/00014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/014 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3841 , H01L2224/13099 , H01L2224/05552 , H01L2924/00
摘要: Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.
摘要翻译: 微型接头中的电迁移会导致微胶囊中的空隙,从而降低了包含微型电池的集成电路的使用寿命。 通过在焊料周围形成铜壳,可能会在微胶囊中增加电迁移寿命。 一个微型块的铜壳接触第二个微型块的铜壳,以封闭微型接头的焊料。 铜壳允许通过微型块的更高的电流密度。 因此,可以以更小的间距制造较小的微胶片,而不会发生电迁移的故障。 此外,铜壳减少了衬底上的微型接头之间的短路或桥接。
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公开(公告)号:US20110193211A1
公开(公告)日:2011-08-11
申请号:US12701201
申请日:2010-02-05
申请人: Arvind Chandrasekaran , Shiqun Gu , Urmi Ray
发明人: Arvind Chandrasekaran , Shiqun Gu , Urmi Ray
IPC分类号: H01L23/538 , H01L21/56 , H01L21/60
CPC分类号: H01L23/3142 , H01L21/563 , H01L23/293 , H01L23/3128 , H01L23/3135 , H01L23/3192 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L2224/0401 , H01L2224/05022 , H01L2224/05147 , H01L2224/0557 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/73203 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2924/00014 , H01L2924/0002 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2224/05552 , H01L2924/00
摘要: A surface preparation method for improved adhesion in an electronic package system. The method of improving adhesion in the electronic package system includes depositing a passivation layer on a bonding surface and roughening at least a portion of the passivation layer. A coating material is deposited on the passivation layer. The bonding surface can be part of a semiconductor or package substrate. The roughening process can be performed by a chemical or mechanical process. In another embodiment, an electronic package system includes a bonding surface of a semiconductor or package substrate. A passivation layer is deposited on the bonding surface and a portion of the passivation layer is roughened for improved adhesion. A coating material is deposited on the roughened portion of the passivation layer.
摘要翻译: 一种用于改善电子封装系统中的附着力的表面处理方法。 提高电子封装系统中的附着力的方法包括在接合表面上沉积钝化层并使钝化层的至少一部分变粗糙。 在钝化层上沉积涂层材料。 接合表面可以是半导体或封装衬底的一部分。 粗化工艺可以通过化学或机械工艺进行。 在另一个实施例中,电子封装系统包括半导体或封装衬底的接合表面。 钝化层沉积在接合表面上,钝化层的一部分被粗糙化以提高粘附力。 在钝化层的粗糙化部分上沉积涂层材料。
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公开(公告)号:US20100127937A1
公开(公告)日:2010-05-27
申请号:US12277447
申请日:2008-11-25
CPC分类号: H01Q1/2283 , G06K19/07775 , G06K19/07779 , H01L23/481 , H01L23/585 , H01L23/645 , H01L23/66 , H01L25/0657 , H01L28/10 , H01L2223/6677 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/19015 , H01Q7/00 , Y10T29/49016 , H01L2924/00
摘要: An antenna structure is integrated in a semiconductor chip. The antenna structure is formed by at least one of: a) one or more through-silicon vias (TSVs), and b) one or more crack stop structures. In certain embodiments, the antenna structure includes an antenna element formed by the TSVs. The antenna structure may further include a directional element formed by the crack stop structure. In certain other embodiments, the antenna structure includes an antenna element formed by the crack stop structure, and the antenna structure may further include a directional element formed by the TSVs.
摘要翻译: 天线结构集成在半导体芯片中。 天线结构由以下至少一种形成:a)一个或多个穿硅通孔(TSV),以及b)一个或多个裂纹停止结构。 在某些实施例中,天线结构包括由TSV形成的天线元件。 天线结构还可以包括由裂纹停止结构形成的方向元件。 在某些其他实施例中,天线结构包括由裂缝停止结构形成的天线元件,并且天线结构还可以包括由TSV形成的定向元件。
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公开(公告)号:US20110012239A1
公开(公告)日:2011-01-20
申请号:US12758311
申请日:2010-04-12
申请人: Shiqun Gu , Urmi Ray , Yiming Li , Arvind Chandrasekaran
发明人: Shiqun Gu , Urmi Ray , Yiming Li , Arvind Chandrasekaran
IPC分类号: H01L29/06 , H01L21/768 , H01L21/311
CPC分类号: H01L23/3192 , H01L21/6836 , H01L23/3142 , H01L24/11 , H01L24/13 , H01L24/94 , H01L2221/6834 , H01L2224/10126 , H01L2224/1147 , H01L2224/1191 , H01L2224/13022 , H01L2224/13099 , H01L2224/16225 , H01L2224/94 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01033 , H01L2924/14 , H01L2924/1433 , H01L2224/11 , H01L2224/03
摘要: A barrier layer deposited on the passivation layer of a semiconductor die decreases adhesion of glue used during stacking of semiconductor dies by altering chemical or structural properties of the passivation layer. During detachment of a carrier wafer from a wafer, the barrier layer reduces glue residue on the wafer by modifying the surface of the passivation layer. The barrier layer may be insulating films such as silicon dioxide, silicon nitride, silicon carbide, polytetrafluoroethylene, organic layers, or epoxy and may be less than two micrometers in thickness. Additionally, the barrier layer may be used to reduce topography of the semiconductor die to decrease adhesion of glues.
摘要翻译: 沉积在半导体管芯的钝化层上的阻挡层通过改变钝化层的化学或结构特性来降低在半导体管芯堆叠期间使用的胶粘附力。 在从晶片分离载体晶片时,阻挡层通过改变钝化层的表面来减少晶片上的胶残余物。 阻挡层可以是诸如二氧化硅,氮化硅,碳化硅,聚四氟乙烯,有机层或环氧树脂之类的绝缘膜,并且其厚度可以小于2微米。 此外,阻挡层可以用于减少半导体管芯的形貌以降低胶粘剂的粘附。
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公开(公告)号:US20100314725A1
公开(公告)日:2010-12-16
申请号:US12483759
申请日:2009-06-12
申请人: Shiqun Gu , Arvind Chandrasekaran , Urmi Ray , Yiming Li
发明人: Shiqun Gu , Arvind Chandrasekaran , Urmi Ray , Yiming Li
IPC分类号: H01L23/00 , H01L21/306 , H01L21/31
CPC分类号: H01L25/0657 , H01L21/76898 , H01L23/562 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00011 , H01L2924/00014 , H01L2224/0401
摘要: A semiconductor component (such as a semiconductor wafer or semiconductor die) includes a substrate having a front side and a back side. The semiconductor die/wafer also includes a stress balance layer on the back side of the substrate. An active layer deposited on the front side of the substrate creates an unbalanced stress in the semiconductor wafer/die. The stress balance layer balances stress in the semiconductor wafer/die. The stress in the stress balance layer approximately equals the stress in the active layer. Balancing stress in the semiconductor component prevents warpage of the semiconductor wafer/die.
摘要翻译: 半导体元件(例如半导体晶片或半导体晶片)包括具有正面和背面的基板。 半导体管芯/晶片还包括在衬底背面的应力平衡层。 沉积在基板的正面上的有源层在半导体晶片/管芯中产生不平衡的应力。 应力平衡层平衡半导体晶片/模具中的应力。 应力平衡层中的应力大致等于有源层中的应力。 在半导体部件中平衡应力可以防止半导体晶片/裸片翘曲。
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公开(公告)号:US20120025362A1
公开(公告)日:2012-02-02
申请号:US12846910
申请日:2010-07-30
申请人: Arvind Chandrasekaran , Shiqun Gu , Zhongping Bao
发明人: Arvind Chandrasekaran , Shiqun Gu , Zhongping Bao
CPC分类号: H01L21/565 , H01L21/568 , H01L21/6836 , H01L23/3121 , H01L23/562 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/73 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L2221/68327 , H01L2221/6834 , H01L2224/14181 , H01L2224/16145 , H01L2224/16221 , H01L2224/73204 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/10253 , H01L2924/15311 , H01L2924/181 , H01L2924/3511 , H01L2224/81 , H01L2224/11 , H01L2924/00
摘要: A method for forming an electrical package to reduce warpage. The method includes providing a wafer and coupling a die thereto. A mold compound material is applied to the wafer such that the mold compound material surrounds the die. The method further includes applying a reinforcing material to the mold compound material. The mold compound material is thereby disposed between the wafer and the reinforcing material.
摘要翻译: 一种用于形成电气封装以减少翘曲的方法。 该方法包括提供晶片并将模具耦合到其上。 将模具复合材料施加到晶片上,使得模具复合材料围绕模具。 该方法还包括将增强材料施加到模具复合材料。 因此,模具复合材料设置在晶片和增强材料之间。
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公开(公告)号:US20120012998A1
公开(公告)日:2012-01-19
申请号:US12837717
申请日:2010-07-16
IPC分类号: H01L23/498 , H01L21/60 , H01L21/768
CPC分类号: H01L24/81 , H01L21/76877 , H01L23/49816 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/742 , H01L25/0657 , H01L25/50 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/0347 , H01L2224/0361 , H01L2224/0401 , H01L2224/051 , H01L2224/05567 , H01L2224/056 , H01L2224/1145 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11472 , H01L2224/1161 , H01L2224/11849 , H01L2224/119 , H01L2224/13017 , H01L2224/13018 , H01L2224/13021 , H01L2224/13023 , H01L2224/13076 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/16058 , H01L2224/16148 , H01L2224/81193 , H01L2224/81203 , H01L2224/81815 , H01L2225/06513 , H01L2924/00013 , H01L2924/00014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/014 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3841 , H01L2224/13099 , H01L2224/05552 , H01L2924/00
摘要: Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.
摘要翻译: 微型接头中的电迁移会导致微胶囊中的空隙,从而降低了包含微型电池的集成电路的使用寿命。 通过在焊料周围形成铜壳,可能会在微胶囊中增加电迁移寿命。 一个微型块的铜壳接触第二个微型块的铜壳,以封闭微型接头的焊料。 铜壳允许通过微型块的更高的电流密度。 因此,可以以更小的间距制造较小的微胶片,而不会发生电迁移的故障。 此外,铜壳减少了衬底上的微型接头之间的短路或桥接。
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