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    Gate structure cut after formation of epitaxial active regions
    81.
    发明授权
    Gate structure cut after formation of epitaxial active regions 有权
    形成外延活性区后的门结构切割

    公开(公告)号：US09559009B2

    公开(公告)日：2017-01-31

    申请号：US14876212

    申请日：2015-10-06

    申请人： International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    发明人： Xiuyu Cai ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Ali Khakifirooz ,  Theodorus E. Standaert ,  Ruilong Xie

    IPC分类号： H01L21/311 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/088 ,  H01L29/08 ,  H01L21/84 ,  H01L29/66

    CPC分类号： H01L21/823437 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785

    摘要： A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.

    摘要翻译： 形成跨越多个半导体材料部分的栅极结构。 源极区域和漏极区域形成在多个半导体材料部分中，并且形成横向围绕栅极结构的栅极间隔物。 通过选择性外延工艺从源极和漏极区域形成外延有源区。 通过切割掩模和蚀刻将栅极结构和栅极间隔物的组装切成多个部分以形成多个栅极组件。 每个门组件包括栅极结构部分和由栅极结构部分横向隔开的两个分离的栅极间隔部分。 可以从栅极间隔物的侧壁的周围去除外延有源区的一部分，以防止外延有源区中的电短路。 可以使用电介质间隔物或电介质衬垫来限制形成金属半导体合金的区域。

    Integrated circuits having gate cap protection and methods of forming the same
    85.
    发明授权
    Integrated circuits having gate cap protection and methods of forming the same 有权
    具有栅极盖保护的集成电路及其形成方法

    公开(公告)号：US09269611B2

    公开(公告)日：2016-02-23

    申请号：US14159944

    申请日：2014-01-21

    申请人： GLOBALFOUNDRIES, Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Daniel Thanh Khae Pham ,  Xiuyu Cai ,  Bala Subramanian Pranatharthi Haran ,  Charan Veera Venkata Satya Surisetty ,  Jin Wook Lee ,  Shom Ponoth ,  David V. Horak

    IPC分类号： H01L29/78 ,  H01L21/768

    CPC分类号： H01L21/76816 ,  H01L21/28247 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Integrated circuits and methods of forming integrated circuits are provided. An integrated circuit includes a gate electrode structure overlying a base substrate. The gate electrode structure includes a gate electrode, with a cap disposed over the gate electrode and sidewall spacers disposed adjacent to sidewalls of the gate electrode structure. A source and drain region are formed in the base substrate aligned with the gate electrode structure. A first dielectric layer is disposed adjacent to the sidewall spacers. The sidewall spacers and the cap have recessed surfaces below a top surface of the first dielectric layer, and a protecting layer is disposed over the recessed surfaces. A second dielectric layer is disposed over the first dielectric layer and the protecting layer. Electrical interconnects are disposed through the first dielectric layer and the second dielectric layer, and the electrical interconnects are in electrical communication with the respective source and drain regions.

    摘要翻译： 提供了形成集成电路的集成电路和方法。 集成电路包括覆盖基底的栅电极结构。 栅极电极结构包括栅电极，栅极设置在栅电极上，侧壁间隔件邻近栅电极结构的侧壁设置。 源极和漏极区域形成在与栅电极结构对准的基底衬底中。 第一电介质层设置成与侧壁间隔物相邻。 侧壁间隔件和盖在第一电介质层的顶表面下方具有凹陷表面，并且保护层设置在凹入表面之上。 第二电介质层设置在第一电介质层和保护层之上。 电互连通过第一介电层和第二介电层设置，并且电互连与相应的源区和漏区电连通。

    Methods of forming finFET semiconductor devices using a replacement gate technique and the resulting devices
    86.
    发明授权
    Methods of forming finFET semiconductor devices using a replacement gate technique and the resulting devices 有权
    使用替代栅极技术形成finFET半导体器件的方法和所得到的器件

    公开(公告)号：US09236480B2

    公开(公告)日：2016-01-12

    申请号：US14044120

    申请日：2013-10-02

    申请人： GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    发明人： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

    IPC分类号： H01L29/78 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

    CPC分类号： H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

    摘要： One method disclosed includes, among other things, forming a raised isolation post structure between first and second fins, wherein the raised isolation post structure partially defines first and second spaces between the first and second fins, respectively, and forming a gate structure around the first and second fins and the raised isolation post structure, wherein at least portions of the gate structure are positioned in the first and second spaces. One illustrative device includes, among other things, first and second fins, a raised isolation post structure positioned between the first and second fins, first and second spaces defined by the fins and the raised isolation post structure, and a gate structure positioned around a portion of the fins and the isolation post structure.

    摘要翻译： 所公开的一种方法包括在第一和第二散热片之间形成凸起的隔离柱结构，其中所述凸起的隔离柱结构分别部分地限定所述第一和第二鳍之间的第一和第二空间，并且形成围绕所述第一和第二鳍的栅极结构 和第二鳍片和凸起的隔离柱结构，其中栅极结构的至少一部分位于第一和第二空间中。 一个说明性装置尤其包括第一和第二散热片，位于第一和第二散热片之间的凸起的隔离柱结构，由翅片和凸起的隔离柱结构限定的第一和第二空间以及围绕一部分 的翅片和隔离柱结构。

    FinFET devices having recessed liner materials to define different fin heights
    88.
    发明授权
    FinFET devices having recessed liner materials to define different fin heights 有权
    FinFET器件具有凹陷的衬垫材料以限定不同的翅片高度

    公开(公告)号：US09000537B2

    公开(公告)日：2015-04-07

    申请号：US14333683

    申请日：2014-07-17

    申请人： Globalfoundries Inc. ,  International Business Machines Corporation

    发明人： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

    IPC分类号： H01L27/02 ,  H01L29/78 ,  H01L29/66

    CPC分类号： H01L27/0207 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

    摘要： One method includes performing an etching process through a patterned mask layer to form trenches in a substrate that defines first and second fins, forming liner material adjacent the first fin to a first thickness, forming liner material adjacent the second fin to a second thickness different from the first thickness, forming insulating material in the trenches adjacent the liner materials and above the mask layer, performing a process operation to remove portions of the layer of insulating material and to expose portions of the liner materials, performing another etching process to remove portions of the liner materials and the mask layer to expose the first fin to a first height and the second fin to a second height different from the first height, performing another etching process to define a reduced-thickness layer of insulating material, and forming a gate structure around a portion of the first and second fin.

    摘要翻译： 一种方法包括通过图案化的掩模层执行蚀刻工艺，以在限定第一和第二鳍片的衬底中形成沟槽，将邻近第一鳍片的衬垫材料形成第一厚度，将与第二鳍片相邻的衬垫材料形成为不同于第二厚度的第二厚度 所述第一厚度在所述沟槽中形成绝缘材料，所述沟槽邻近所述衬垫材料并且在所述掩模层上方，执行处理操作以去除所述绝缘材料层的部分并暴露所述衬垫材料的部分，执行另一蚀刻工艺以去除部分 所述衬垫材料和所述掩模层将所述第一翅片暴露于第一高度，并且所述第二鳍片具有不同于所述第一高度的第二高度，执行另一蚀刻工艺以限定绝缘材料的厚度减薄层，以及形成栅极结构 围绕第一和第二鳍的一部分。

    SELF-ALIGNED DIELECTRIC ISOLATION FOR FINFET DEVICES
    89.
    发明申请
    SELF-ALIGNED DIELECTRIC ISOLATION FOR FINFET DEVICES 有权
    用于FINFET器件的自对准介电隔离

    公开(公告)号：US20150061040A1

    公开(公告)日：2015-03-05

    申请号：US14538401

    申请日：2014-11-11

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

    发明人： Marc Adam Bergendahl ,  Kangguo Cheng ,  David Vaclav Horak ,  Ali Khakifirooz ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Chih-Chao Yang ,  Charles William Koburger, III ,  Xiuyu Cai ,  Ruilong Xie

    IPC分类号： H01L27/088 ,  H01L29/06

    CPC分类号： H01L27/0886 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7855

    摘要： Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.

    摘要翻译： 本发明的实施例提供一种形成半导体结构的方法。 该方法包括在衬底的顶部上形成一组器件特征; 在所述组装置特征的顶部直接形成第一介电层，并在所述基板的顶部上形成第一电介质层，从而产生从所述基板的顶表面测量的所述第一电介质层的高度分布，所述高度分布与所述基板的图案相关联 完全围绕设备特征的绝缘结构; 以及在由所述图案限定的区域中形成第二电介质层以形成所述绝缘结构。 还公开了通过该方法形成的结构。

    METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A PROTECTED GATE CAP LAYER AND THE RESULTING DEVICE
    90.
    发明申请
    METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A PROTECTED GATE CAP LAYER AND THE RESULTING DEVICE 有权
    形成具有保护盖板层和结构设备的半导体器件的方法

    公开(公告)号：US20150041869A1

    公开(公告)日：2015-02-12

    申请号：US14526126

    申请日：2014-10-28

    申请人： GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    发明人： Daniel Pham ,  Xiuyu Cai ,  Balasubramanian Pranatharthiharan ,  Pranita Kulkarni

    IPC分类号： H01L29/423 ,  H01L29/51

    CPC分类号： H01L29/42364 ,  H01L21/28247 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78

    摘要： One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material.

    摘要翻译： 本文公开的一种方法包括形成封装并保护栅极盖层的第一和第二栅极盖保护层。 本文公开的新型晶体管器件包括位于半导体衬底上方的栅极结构，邻近栅极结构定位的间隔结构，位于衬底上方并围绕间隔结构的绝缘材料层，位于栅极结构之上的栅极盖层， 所述间隔结构以及封装所述栅极盖层的栅极帽保护材料，其中所述栅极盖保护材料的部分位于所述栅极盖层和所述栅极结构之间，所述间隔物结构和所述绝缘材料层。