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193 条记录 (耗时 0.02 秒)

    Self-aligned dielectric isolation for FinFET devices
    2.
    发明授权
    Self-aligned dielectric isolation for FinFET devices 有权
    FinFET器件的自对准介质隔离

    公开(公告)号：US08941156B2

    公开(公告)日：2015-01-27

    申请号：US13735315

    申请日：2013-01-07

    申请人： International Business Machines Corporation ,  GlobalFoundries, Inc.

    发明人： Marc Adam Bergendahl ,  Kangguo Cheng ,  David Vaclav Horak ,  Ali Khakifirooz ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Chih-Chao Yang ,  Charles William Koburger, III ,  Xiuyu Cai ,  Ruilong Xie

    IPC分类号： H01L29/78

    CPC分类号： H01L27/0886 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7855

    摘要： Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.

    摘要翻译： 本发明的实施例提供一种形成半导体结构的方法。 该方法包括在衬底的顶部上形成一组器件特征; 在所述组装置特征的顶部直接形成第一介电层，并在所述基板的顶部上形成第一电介质层，从而产生从所述基板的顶表面测量的所述第一电介质层的高度分布，所述高度分布与所述基板的图案相关联 完全围绕设备特征的绝缘结构; 以及在由所述图案限定的区域中形成第二电介质层以形成所述绝缘结构。 还公开了通过该方法形成的结构。

    Integrated circuits and methods for fabricating integrated circuits having metal gate electrodes
    3.
    发明授权
    Integrated circuits and methods for fabricating integrated circuits having metal gate electrodes 有权
    用于制造具有金属栅电极的集成电路的集成电路和方法

    公开(公告)号：US08835244B2

    公开(公告)日：2014-09-16

    申请号：US13773397

    申请日：2013-02-21

    申请人： GlobalFoundries, Inc. ,  International Business Machines Corporation

    发明人： Ruilong Xie ,  Chanro Park ,  Shom Ponoth

    IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L29/788

    CPC分类号： H01L29/66477 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/788

    摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a sacrificial gate structure over a semiconductor substrate. The sacrificial gate structure includes two spacers and sacrificial gate material between the two spacers. The method recesses a portion of the sacrificial gate material between the two spacers. Upper regions of the two spacers are etched while using the sacrificial gate material as a mask. The method includes removing a remaining portion of the sacrificial gate material and exposing lower regions of the two spacers. A first metal is deposited between the lower regions of the two spacers. A second metal is deposited between the upper regions of the two spacers.

    摘要翻译： 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，用于制造集成电路的方法包括在半导体衬底上提供牺牲栅极结构。 牺牲栅极结构在两个间隔物之间​​包括两个间隔物和牺牲栅极材料。 该方法将牺牲栅极材料的一部分凹入两个间隔物之间​​。 在使用牺牲栅极材料作为掩模的同时蚀刻两个间隔物的上部区域。 该方法包括去除牺牲栅极材料的剩余部分并暴露两个间隔物的下部区域。 第一金属沉积在两个间隔物的下部区域之间。 第二金属沉积在两个间隔物的上部区域之间。

    CONTACT FORMATION FOR ULTRA-SCALED DEVICES
    6.
    发明申请
    CONTACT FORMATION FOR ULTRA-SCALED DEVICES 有权
    超声波设备的接触形式

    公开(公告)号：US20140339629A1

    公开(公告)日：2014-11-20

    申请号：US13894513

    申请日：2013-05-15

    申请人： International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    发明人： Ruilong Xie ,  Shom Ponoth ,  David V. Horak ,  Balasubramanian Pranatharthiharan

    IPC分类号： H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/7827 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/66666

    摘要： Embodiments of the invention provide approaches for forming gate and source/drain (S/D) contacts. Specifically, the semiconductor device includes a gate transistor formed over a substrate, a S/D contact formed over a trench-silicide (TS) layer and positioned adjacent the gate transistor, and a gate contact formed over the gate transistor, wherein at least a portion of the gate contact is aligned over the TS layer. This structure enables contact with the TS layer, thereby decreasing the distance between the gate contact and the source/drain, which is desirable for ultra-area-scaling.

    摘要翻译： 本发明的实施例提供了用于形成栅极和源极/漏极（S / D）触点的方法。 具体地，半导体器件包括形成在衬底上的栅极晶体管，形成在沟槽硅化物（TS）层上并且邻近栅极晶体管定位的S / D接触，以及形成在栅极晶体管上的栅极接触，其中至少一个 栅极触点的一部分在TS层上对齐。 这种结构使得能够与TS层接触，从而减小栅极接触和源极/漏极之间的距离，这对于超区域缩放是期望的。

    PREVENTION OF FIN EROSION FOR SEMICONDUCTOR DEVICES
    8.
    发明申请
    PREVENTION OF FIN EROSION FOR SEMICONDUCTOR DEVICES 有权
    防止半导体器件的腐蚀

    公开(公告)号：US20140124840A1

    公开(公告)日：2014-05-08

    申请号：US13670674

    申请日：2012-11-07

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

    发明人： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Shom Ponoth ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Xiuyu Cai ,  Ruilong Xie

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/311

    CPC分类号： H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    摘要： A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

    摘要翻译： 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一​​次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。

    Integrated circuits having gate cap protection and methods of forming the same
    10.
    发明授权
    Integrated circuits having gate cap protection and methods of forming the same 有权
    具有栅极盖保护的集成电路及其形成方法

    公开(公告)号：US09269611B2

    公开(公告)日：2016-02-23

    申请号：US14159944

    申请日：2014-01-21

    申请人： GLOBALFOUNDRIES, Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Daniel Thanh Khae Pham ,  Xiuyu Cai ,  Bala Subramanian Pranatharthi Haran ,  Charan Veera Venkata Satya Surisetty ,  Jin Wook Lee ,  Shom Ponoth ,  David V. Horak

    IPC分类号： H01L29/78 ,  H01L21/768

    CPC分类号： H01L21/76816 ,  H01L21/28247 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Integrated circuits and methods of forming integrated circuits are provided. An integrated circuit includes a gate electrode structure overlying a base substrate. The gate electrode structure includes a gate electrode, with a cap disposed over the gate electrode and sidewall spacers disposed adjacent to sidewalls of the gate electrode structure. A source and drain region are formed in the base substrate aligned with the gate electrode structure. A first dielectric layer is disposed adjacent to the sidewall spacers. The sidewall spacers and the cap have recessed surfaces below a top surface of the first dielectric layer, and a protecting layer is disposed over the recessed surfaces. A second dielectric layer is disposed over the first dielectric layer and the protecting layer. Electrical interconnects are disposed through the first dielectric layer and the second dielectric layer, and the electrical interconnects are in electrical communication with the respective source and drain regions.

    摘要翻译： 提供了形成集成电路的集成电路和方法。 集成电路包括覆盖基底的栅电极结构。 栅极电极结构包括栅电极，栅极设置在栅电极上，侧壁间隔件邻近栅电极结构的侧壁设置。 源极和漏极区域形成在与栅电极结构对准的基底衬底中。 第一电介质层设置成与侧壁间隔物相邻。 侧壁间隔件和盖在第一电介质层的顶表面下方具有凹陷表面，并且保护层设置在凹入表面之上。 第二电介质层设置在第一电介质层和保护层之上。 电互连通过第一介电层和第二介电层设置，并且电互连与相应的源区和漏区电连通。