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公开(公告)号：US20050049809A1
公开(公告)日：2005-03-03
申请号：US10915345
申请日：2004-08-11
IPC分类号： G01R31/316 , G01R35/00 , G06F19/00
CPC分类号： G01R35/005 , G01R31/316
摘要： An analog circuit automatic calibration system for calibrating an object circuit that is an analog circuit having a characteristic changing with an input set value. The system includes: a set value storage section for storing a value and outputting the value to the object circuit as the set value; a characteristic detection section for detecting the characteristic of the object circuit; a first characteristic change section for determining the set value so that the characteristic of the object circuit is optimized; a second characteristic change section for updating the set value so that the characteristic of the object circuit is maintained, using an algorithm different from that used in the first characteristic change section; and a selector for selecting either one of the outputs of the first and second characteristic sections to enable the selected one to be stored in the set value storage section.
摘要翻译： 一种模拟电路自动校准系统，用于校准作为具有随着输入设定值变化的特性的模拟电路的目标电路。 该系统包括：设定值存储部分，用于存储值并将该值输出到对象电路作为设定值; 用于检测所述目标电路的特性的特性检测部分; 用于确定所述设定值使得所述对象电路的特性被优化的第一特征变化部分; 第二特征变化部，使用与第一特征变化部中使用的算法不同的算法来更新设定值，使得保持对象电路的特性; 以及选择器，用于选择第一和第二特征部分的输出之一，以使所选择的一个存储在设定值存储部分中。
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公开(公告)号：US20050047511A1
公开(公告)日：2005-03-03
申请号：US10914177
申请日：2004-08-10
申请人： Shiro Dosho , Yusuke Tokunaga
发明人： Shiro Dosho , Yusuke Tokunaga
IPC分类号： H03K17/00 , H03K17/687 , H03K19/0175 , H04L25/02 , H04L25/06 , H04L25/49 , H04L27/00 , H04L25/00
CPC分类号： H04L25/062
摘要： A data transmitter receives a reference current from a current generator and outputs as a current signal a current obtained by multiplying the reference current by a given number in accordance with the value of transmit data. A data receiver, on the other hand, receives the current signal from the data transmitter to generate a receive signal, while receiving a reference current from the current generator to generate a reference signal which is necessary for level determination of the receive signal. In this manner, the reference currents, from which the current signal and the reference signal are respectively generated, are supplied from the current generator that is used in common by the data transmitter and the data receiver.
摘要翻译： 数据发送器从电流发生器接收参考电流，并根据发送数据的值，将参考电流乘以给定数字而获得的电流作为电流信号输出。 另一方面，数据接收器从数据发送器接收当前信号以产生接收信号，同时从当前发生器接收参考电流以产生对于接收信号的电平确定所必需的参考信号。 以这种方式，从数据发送器和数据接收器共同使用的电流发生器提供从其分别产生电流信号和参考信号的参考电流。
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公开(公告)号：US06801587B2
公开(公告)日：2004-10-05
申请号：US09741086
申请日：2000-12-21
申请人： Shiro Dosho
发明人： Shiro Dosho
IPC分类号： H04L2706
摘要： A data extracting circuit extracts data much more accurately at a much higher response speed. A clock transfer section propagates an input clock signal through unit delay devices thereof. An edge detecting section locates an edge of the clock signal, which edge is being propagated through the clock transfer section, for a time represented by a given edge of an input data signal. In response to an edge detection signal indicating the clock signal edge located, a clock selecting section selects one of outputs of the delay devices, and presents the output as a clock input to a latch.
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公开(公告)号：US5828717A
公开(公告)日：1998-10-27
申请号：US624960
申请日：1996-03-27
申请人： Keiichi Kusumoto , Shiro Dosho , Yutaka Terada , Akira Matsuzawa
发明人： Keiichi Kusumoto , Shiro Dosho , Yutaka Terada , Akira Matsuzawa
IPC分类号： G01R29/027 , G01C21/00
CPC分类号： G01R29/0273
摘要： There is provided a time counting circuit for measuring a pulse spacing of a pulse signal with high accuracy and with low power consumption. An inverter ring composed of an odd number of inverters connected in a ring oscillates and one signal transition occurs after another as though seemingly circulating around the inverter ring. Holding circuits connected to respective output terminals of the inverters composing the inverter ring output, on the rising edge of a pulse signal to be measured, signals outputted from the inverters at the same time. The outputted signals are then converted by a signal converting circuit to numeric data. A counter circuit connected to the output terminal of one of the inverters composing the inverter ring counts the number of circulations of signal transition. A time-difference operating circuit corrects the numeric data outputted from the signal converting circuit based on the number of circulations of signal transition outputted from the counter circuit to provide time data, while calculating and outputting the pulse spacing of the pulse signal to be measured.
摘要翻译： 提供了一种用于以高精度和低功耗测量脉冲信号的脉冲间隔的时间计数电路。 由连接在环上的奇数个反相器组成的逆变器环振荡，并且一个信号转换发生在似乎在逆变器环周围似乎循环。 连接到构成逆变器环的逆变器的各个输出端子的保持电路在待测脉冲信号的上升沿同时输出从逆变器输出的信号。 然后，输出的信号由信号转换电路转换成数字数据。 连接到构成逆变器环的逆变器之一的输出端的计数器电路对信号转换的循环数进行计数。 时差操作电路根据从计数器电路输出的信号转换的循环数来校正从信号转换电路输出的数字数据，以提供时间数据，同时计算并输出要测量的脉冲信号的脉冲间隔。
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公开(公告)号：US5822236A
公开(公告)日：1998-10-13
申请号：US863209
申请日：1997-05-27
CPC分类号： G11C27/04 , G11C27/00 , H03H19/004 , H04N9/78
摘要： The invention provides an analog FIFO memory from which a written analog signal can be accurately read by eliminating errors in the analog signal between the write operation and the read operation. Prior to the read operation for reading the analog signal from a memory cell through a memory bus, a reset operation for setting the memory bus at a predetermined potential is conducted so as to remove a charge stored in a parasitic capacitance of the memory bus. The input terminal of a read circuit is set at a predetermined potential, with a write circuit disconnected from the memory bus by using an input circuit and with the read circuit connected with the memory bus by using an output circuit. In this manner, the memory bus is set at the predetermined potential, and the charge stored in the parasitic capacitance is discharged. At this point, a switch in each memory cell is in an off-state, and hence, a charge corresponding to the analog signal can be retained in the memory cell.
摘要翻译： 本发明提供了一种模拟FIFO存储器，通过消除写入操作和读取操作之间的模拟信号中的错误，可以准确地读取写入的模拟信号。 在从存储器单元通过存储器总线读取模拟信号的读取操作之前，进行用于将存储器总线设置在预定电位的复位操作，以便消除存储在存储器总线的寄生电容中的电荷。 读取电路的输入端子通过使用输入电路和与存储器总线连接的读取电路通过使用输出电路将写入电路从存储器总线断开而被设置在预定电位。 以这种方式，将存储器总线设置在预定电位，并且存储在寄生电容中的电荷被放电。 此时，每个存储单元中的开关处于截止状态，因此可以将与模拟信号相对应的电荷保留在存储单元中。
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公开(公告)号：US5550544A
公开(公告)日：1996-08-27
申请号：US200493
申请日：1994-02-23
申请人： Shiro Sakiyama , Shiro Dosho , Masakatsu Maruyama , Hiroyuki Nakahira , Toshiyuki Shono , Akira Matsuzawa
发明人： Shiro Sakiyama , Shiro Dosho , Masakatsu Maruyama , Hiroyuki Nakahira , Toshiyuki Shono , Akira Matsuzawa
摘要： The present invention provides a first-order delta-sigma AD converter adapted to conduct noise shaping and having a quantizer arranged such that, when the amplitude of an input signal entered into the quantizer is small, the amplitude of a difference signal between the input signal entered into the quantizer and an output signal therefrom, is small. It is therefore possible to achieve an efficient AD- or DA-converter reduced in power consumption, which satisfies the transmission characteristics of the specifications of CCITT G.714 based on a method of PCM-encoding an audio frequency band signal stipulated in the specifications of CCITT G.711.
摘要翻译： 本发明提供了一种适用于进行噪声整形并具有量化器的一级Δ-ΣAD转换器，其被布置为使得当输入到量化器的输入信号的幅度较小时，输入信号之间的差信号的幅度 进入量化器并且其输出信号很小。 因此，可以实现功率消耗降低的有效的AD转换器或DA转换器，该功率消耗满足CCITT G.714的规格的传输特性，该方法基于对编码 CCITT G.711。
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87.发明授权
公开(公告)号：US5495296A
公开(公告)日：1996-02-27
申请号：US59561
申请日：1993-05-12
申请人： Shiro Dosho , Tatsuro Juri
发明人： Shiro Dosho , Tatsuro Juri
IPC分类号： H04N5/14 , H03H17/00 , H04N7/00 , H04N7/46 , H04N9/804 , H04N9/808 , H04N9/87 , H04N11/04 , H04N11/16 , H04N11/22 , H04N19/00 , H04N19/423 , H04N19/426 , H04N19/59
CPC分类号： H04N19/59 , H04N11/22 , H04N9/8042 , H04N9/87
摘要： In order to thin an input signal a second multiplexer is switched to output an output of a first adder and a third multiplexer is switched to output an output of a second adder, and a first multiplexer is alternatively switched at every line. A delay circuit memorizes the sum of the two preceding input signals, and the second adder outputs at every other line the sum of image data of a present line and the two preceding lines. To interpolate an input signal, the second multiplexer is switched to output the output of the delay circuit, the first multiplexer is alternatively switched to output either the input signal or the output of the second multiplexer, and the second multiplexer is alternatively switched to output either the output of the first adder or the output of the delay circuit. Thus, the delay circuit outputs at every other line the sum of the two preceding input signals. Because only one delay circuit is needed the size of the perpendicular thinning/interpolation circuit for an image signal is reduced.
摘要翻译： 为了使输入信号变薄，第二多路复用器被切换以输出第一加法器的输出，并且第三多路复用器被切换以输出第二加法器的输出，并且第一多路复用器在每一行交替切换。 延迟电路存储前两个输入信号的和，并且第二加法器在每隔一行输出当前行和前两行的图像数据之和。 为了插入输入信号，第二多路复用器被切换以输出延迟电路的输出，第一多路复用器被交替切换以输出第二多路复用器的输入信号或输出，并且第二多路复用器交替切换以输出 第一加法器的输出或延迟电路的输出。 因此，延迟电路在每隔一行输出前面两个输入信号的和。 因为只需要一个延迟电路，所以减小图像信号的垂直细化/插值电路的尺寸。
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88.发明授权Reference frequency generation circuit, semiconductor integrated circuit, and electronic device 有权参考频率发生电路，半导体集成电路和电子设备公开(公告)号：US08212624B2
公开(公告)日：2012-07-03
申请号：US13022029
申请日：2011-02-07
IPC分类号： H02K3/26
CPC分类号： H03K4/501
摘要： An oscillator circuit increases and reduces signal levels of first and second oscillation signals in a complementary manner in response to a transition of a signal level of a reference clock. An oscillation control circuit compares each of the signal levels of the first and second oscillation signals to a comparison voltage, and causes the signal level of the reference clock to transition according to results of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced.
摘要翻译： 响应于参考时钟的信号电平的转变，振荡器电路以互补的方式增加并降低第一和第二振荡信号的信号电平。 振荡控制电路将第一和第二振荡信号的每个信号电平与比较电压进行比较，并根据比较结果使参考时钟的信号电平转变。 参考控制电路增加或减小比较电压，使得与第一和第二振荡信号的相应摆动成比例的中间信号的信号电平与参考电压之间的差减小。
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公开(公告)号：US08040168B2
公开(公告)日：2011-10-18
申请号：US11188855
申请日：2005-07-26
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata
CPC分类号： H02M3/07
摘要： The charge pump circuit includes: a first switch for controlling either one of push operation and pull operation based on a first control signal; a current mirror circuit composed of a transistor different in attribute from the first switch; and a second switch composed of a transistor same in characteristic as a transistor constituting the first switch, for controlling input of a current into the current mirror circuit based on a second control. The other operation, the push operation or the pull operation, is performed with a current output from the current mirror circuit.
摘要翻译： 电荷泵电路包括：第一开关，用于基于第一控制信号控制按压操作和拉动操作中的任一个; 由与第一开关属性不同的晶体管构成的电流镜电路; 以及由构成第一开关的晶体管的特性相同的晶体管构成的第二开关，用于基于第二控制来控制输入到电流镜像电路的电流。 另一个操作，推动操作或拉动操作由电流镜电路的电流输出执行。
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公开(公告)号：US08013650B2
公开(公告)日：2011-09-06
申请号：US11514151
申请日：2006-09-01
IPC分类号： H03H11/16
CPC分类号： H03K5/13 , H03K5/15013 , H03K2005/00052 , H03K2005/00273
摘要： A phase adjustment circuit includes first to nth two-phase adjustment circuits. Each two-phase adjustment circuit includes a first logic circuit for performing logical sum of two input signals, a second logic circuit for performing logical product of the two input signals, a first delay circuit having a signal delay equal to that of the second logic circuit and configured to delay a signal output from the first logic circuit, and a second delay circuit having a signal delay equal to that of the first logic circuit and configured to delay a signal output from the second logic circuit. Two signals output from two of the two-phase adjustment circuits in a certain stage are input into one of the two-phase adjustment circuits in the next stage.
摘要翻译： 相位调整电路包括第一至第二相位调整电路。 每个两相调节电路包括用于执行两个输入信号的逻辑和的第一逻辑电路，用于执行两个输入信号的逻辑积的第二逻辑电路，具有等于第二逻辑电路的信号延迟的信号延迟的第一延迟电路 并且被配置为延迟从第一逻辑电路输出的信号;以及第二延迟电路，其具有等于第一逻辑电路的信号延迟的信号延迟，并且被配置为延迟从第二逻辑电路输出的信号。 在一定阶段从两相调节电路中输出的两个信号在下一级输入到两相调节电路之一。
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