公开(公告)号：US20150295299A1

公开(公告)日：2015-10-15

申请号：US14574363

申请日：2014-12-17

Applicant: Texas Instruments Incorporated

Inventor： Juan Alejandro Herbsommer

IPC: H01P5/12 ,  H01P3/16

CPC classification number: H01P1/213 ,  H01P1/2002 ,  H01P3/122 ,  H01P3/16 ,  H01P5/12

Abstract: Signals on a dielectric waveguide are filtered to pass or block selected frequencies. A combined signal is received in the DWG, wherein the combined signal comprises at least a first frequency signal with a first wavelength and a second frequency signal with a second wavelength. The combined signal is split into a first portion and a second portion. The first portion of the combined signal is delayed by an amount of delay time to form a delayed first portion. The delayed first portion is joined with the received combined signal to form a filtered signal such that the first frequency signal is enhanced by constructive interference while the second frequency signal is diminished by destructive interference. A portion of the filtered signal is provided to a receiver, whereby the amplitude of the second frequency signal is attenuated in the filtered signal.

Abstract translation: 对介质波导上的信号进行滤波以通过或阻止选定的频率。 在DWG中接收组合信号，其中组合信号至少包括具有第一波长的第一频率信号和具有第二波长的第二频率信号。 组合信号被分成第一部分和第二部分。 组合信号的第一部分延迟延迟时间的量以形成延迟的第一部分。 延迟的第一部分与接收到的组合信号相结合以形成经滤波的信号，使得第一频率信号通过相长干扰而增强，而第二频率信号被破坏性干扰减小。 经滤波的信号的一部分被提供给接收器，由此第二频率信号的幅度在滤波信号中衰减。

公开(公告)号：US20150295298A1

公开(公告)日：2015-10-15

申请号：US14555545

申请日：2014-11-26

Applicant: Texas Instruments Incorporated

Inventor： Robert Floyd Payne ,  Gerd Schuppener ,  Juan Alejandro Herbsommer

IPC: H01P3/16 ,  H01Q19/18 ,  H01P11/00 ,  H01Q1/50

CPC classification number: H01P3/16 ,  H01P11/006

Abstract: A digital system has a dielectric core waveguide that is formed within a multilayer substrate. The dielectric waveguide has a longitudinal dielectric core member formed in the core layer having two adjacent longitudinal sides each separated from the core layer by a corresponding slot portion formed in the core layer The dielectric core member has the first dielectric constant value. A cladding surrounds the dielectric core member formed by a top layer and the bottom layer infilling the slot portions of the core layer. The cladding has a dielectric constant value that is lower than the first dielectric constant value.

Abstract translation: 数字系统具有形成在多层基板内的介质芯波导。 电介质波导具有形成在芯层中的纵向介质芯构件，其具有两个相邻的纵向侧，每个纵向侧通过形成在芯层中的对应的狭缝部分与芯层分离。介电芯构件具有第一介电常数值。 包层包围由顶层形成的介质芯构件，底层填充芯层的槽部分。 包层具有低于第一介电常数值的介电常数值。

公开(公告)号：US20150293039A1

公开(公告)日：2015-10-15

申请号：US14586842

申请日：2014-12-30

Applicant: Texas Instruments Incorporated

Inventor： Juan Alejandro Herbsommer ,  Robert Floyd Payne

IPC: G01N22/00

CPC classification number: G01N22/00

Abstract: A dielectric waveguide (DWG) may be used to identify a composition of a material that is in contact with the DWG. A radio frequency (RF) signal is transmitted into a dielectric waveguide located in contact with the material. The RF signal is received after it passes through the DWG. An insertion loss of the DWG is determined. The presence of the material may be inferred when the insertion loss exceeds a threshold value. The composition of the material may be inferred based on a correlation with the insertion loss. Alternatively, a volume of the material may be inferred based on a correlation with the insertion loss.

Abstract translation: 介质波导（DWG）可用于识别与DWG接触的材料的组成。 射频（RF）信号被传输到与材料接触的介质波导中。 RF信号在通过DWG之后被接收。 确定DWG的插入损耗。 当插入损耗超过阈值时，可以推断材料的存在。 可以基于与插入损耗的相关性推断材料的组成。 或者，可以基于与插入损耗的相关性来推断材料的体积。

公开(公告)号：US20140368301A1

公开(公告)日：2014-12-18

申请号：US14285616

申请日：2014-05-22

Applicant: Texas Instruments Incorporated

Inventor： Juan Alejandro Herbsommer ,  Baher Haroun

IPC: H01P3/16

CPC classification number: H01P3/16 ,  H01P3/122

Abstract: A dielectric waveguide (DWG) has a dielectric core member that has a length L and an oblong cross section. The core member has a first dielectric constant value. A dielectric cladding surrounds the dielectric core member; the cladding has a second dielectric constant value that is lower than the first dielectric constant. A conductive shield layer surrounds a portion of the dielectric cladding.

Abstract translation: 电介质波导（DWG）具有长度L和长方形横截面的电介质芯构件。 芯构件具有第一介电常数值。 电介质包层围绕介电芯构件; 所述包层具有低于所述第一介电常数的第二介电常数值。 导电屏蔽层围绕电介质包层的一部分。

公开(公告)号：US20140306332A1

公开(公告)日：2014-10-16

申请号：US14181966

申请日：2014-02-17

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Brian Ashley Carpenter ,  Osvaldo Jorge Lopez ,  Juan Alejandro Herbsommer ,  Jonathan Noquil

IPC: H01L23/495 ,  H01L21/50 ,  H01L23/48

CPC classification number: H01L23/49575 ,  H01L21/50 ,  H01L21/561 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/84 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/20752

Abstract: A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical input terminal (203); a first FET chip (sync chip, 220) with its source terminal affixed to the leadframe and on its opposite surface a first drain terminal (221) positioned adjacent to a second drain terminal (222), the drain terminals connected respectively by a first (241) and a second (242) metal clip to a first (204) and second (205) output lead; a second FET chip (control chip, 211), positioned vertically over the first drain terminal, with its source terminal attached onto the first clip; a third FET chip (control chip, 212), positioned vertically over the second drain terminal, with its source terminal attached onto the second clip; and the drain terminals (213, 214) of the second and third chips attached onto a third metal clip (260) connected to the input lead (203).

Abstract translation: 一种封装的多输出转换器（200），包括具有作为接地端子的芯片焊盘（201）的引线框和包括所述电输入端子（203）的多个引线（202）; 第一FET芯片（同步芯片，220），其源极端子固定到引线框架，并且在其相对表面上与第二漏极端子（222）相邻定位的第一漏极端子（221），漏极端子分别由第一（ 241）和第二（242）金属夹到第一（204）和第二（205）输出引线; 位于第一漏极端子上方的第二FET芯片（控制芯片211），其源极端子附接到第一夹子上; 第三FET芯片（控制芯片212），其垂直地位于第二漏极端子上，其源极端子附接到第二夹子上; 和连接到连接到输入引线（203）的第三金属夹（260）上的第二和第三芯片的漏极端子（213,214）。

公开(公告)号：US20140287701A1

公开(公告)日：2014-09-25

申请号：US13854939

申请日：2013-04-01

Applicant: Texas Instruments Incorporated

Inventor： Juan Alejandro Herbsommer ,  Eunyoung Seok ,  Baher Haroun

IPC: H01Q1/50 ,  H04B1/40 ,  H01Q19/10

CPC classification number: H01P3/16 ,  G02B6/4416 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01P3/121 ,  H01P3/165 ,  H01P5/00 ,  H01P5/087 ,  H01P5/107 ,  H01P5/184 ,  H01P11/001 ,  H01P11/002 ,  H01Q1/50 ,  H01Q19/108 ,  H01Q19/30 ,  H04B1/40 ,  Y10T29/49016 ,  Y10T29/49826

Abstract: An electronic device has a multilayer substrate that has an interface surface configured for interfacing to a dielectric waveguide. A conductive layer on the substrate is etched to form a dipole antenna disposed adjacent the interface surface to provide coupling to the dielectric waveguide. A reflector structure is formed in the substrate adjacent the dipole antenna opposite from the interface surface.

Abstract translation: 电子设备具有多层基板，该多层基板具有被配置为与电介质波导连接的界面。 蚀刻衬底上的导电层以形成邻近界面表面设置的偶极天线，以提供与介质波导的耦合。 反射器结构形成在与界面表面相对的偶极子天线附近的衬底中。

公开(公告)号：US11955692B2

公开(公告)日：2024-04-09

申请号：US17515315

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Juan Alejandro Herbsommer

IPC: H01Q1/22 ,  H01Q1/36 ,  H01Q1/46 ,  H01Q9/06

CPC classification number: H01Q1/2283 ,  H01Q1/364 ,  H01Q1/46 ,  H01Q9/065

Abstract: A described example includes: a semiconductor die mounted to a die pad of a package substrate, the semiconductor die having bond pads on a device side surface facing away from the die pad; bond wires coupling the bond pads of the semiconductor die to leads of the package substrate, the leads spaced from the die pad; an antenna positioned over the device side surface of the semiconductor die and having a feed line coupled between the antenna and a device side surface of the semiconductor die; and mold compound covering the semiconductor die, the bond wires, a portion of the leads, and the die side surface of the die pad, a portion of the antenna exposed from the mold compound.

公开(公告)号：US11837775B2

公开(公告)日：2023-12-05

申请号：US17539110

申请日：2021-11-30

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Juan Alejandro Herbsommer

IPC: H01Q1/22 ,  H01L23/31 ,  H05K1/02 ,  H01L23/66

CPC classification number: H01Q1/2283 ,  H01L23/3114 ,  H01L23/66 ,  H05K1/0237 ,  H01L2223/6677

Abstract: A described example includes: an antenna formed in a first conductor layer on a device side surface of a multilayer package substrate, the multilayer package substrate including conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers, the multilayer package substrate having a board side surface opposite the device side surface; and a semiconductor die mounted to the device side surface of the multilayer package substrate spaced from and coupled to the antenna.

公开(公告)号：US20230327678A1

公开(公告)日：2023-10-12

申请号：US18334312

申请日：2023-06-13

Applicant: Texas Instruments Incorporated

Inventor： Juan Alejandro Herbsommer ,  Nikita Mahjabeen ,  Hassan Omar Ali ,  Meysam Moallem

IPC: H03L7/26 ,  H01P3/00 ,  H01Q1/22 ,  G06F1/12 ,  H05K1/02 ,  H01Q1/38 ,  G04F5/14 ,  H04B1/40 ,  H01Q13/18 ,  H01P5/107 ,  G01N29/44 ,  H01P3/12

CPC classification number: H03L7/26 ,  H01P3/003 ,  H01Q1/2283 ,  G06F1/12 ,  H05K1/0243 ,  H01Q1/38 ,  H01P3/006 ,  G04F5/145 ,  H04B1/40 ,  H01Q13/18 ,  H01P5/107 ,  G01N29/44 ,  H01P3/121

Abstract: In a described example, an apparatus includes: a package substrate having a device side surface and a board side surface opposite the device side surface; a physics cell mounted on the device side surface having a first end and a second end; a first opening extending through the package substrate and lined with a conductor, aligned with the first end; a second opening extending through the package substrate and lined with the conductor, aligned with the second end; a millimeter wave transmitter module on the board side, having a millimeter wave transfer structure including a transmission line coupled to an antenna aligned with the first opening; and a millimeter wave receiver module mounted on the board side surface of the package substrate and having a millimeter wave transfer structure including a transmission line coupled to an antenna for receiving millimeter wave signals, aligned with the second opening.

公开(公告)号：US20220344796A1

公开(公告)日：2022-10-27

申请号：US17539110

申请日：2021-11-30

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Juan Alejandro Herbsommer

IPC: H01Q1/22 ,  H01L23/31 ,  H01L23/66 ,  H05K1/02

Abstract: A described example includes: an antenna formed in a first conductor layer on a device side surface of a multilayer package substrate, the multilayer package substrate including conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers, the multilayer package substrate having a board side surface opposite the device side surface; and a semiconductor die mounted to the device side surface of the multilayer package substrate spaced from and coupled to the antenna.