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    Multicore Bus Architecture With Wire Reduction and Physical Congestion Minimization Via Shared Transaction Channels
    84.
    发明申请
    Multicore Bus Architecture With Wire Reduction and Physical Congestion Minimization Via Shared Transaction Channels 审中-公开
    通过共享事务通道减少线路和物理拥塞最小化的多核总线架构

    公开(公告)号：US20160124890A1

    公开(公告)日：2016-05-05

    申请号：US14530266

    申请日：2014-10-31

    Applicant: Texas Instruments Incorporated

    Inventor： David M. Thompson ,  Timothy Anderson ,  Joseph Zbiciak ,  Abhijeet A. Chachad ,  Kai Chirca ,  Matthew D. Pierson

    IPC: G06F13/42 ,  G06F13/362

    CPC classification number: G06F13/4252 ,  G06F13/362

    Abstract: The Multicore Bus Architecture (MBA) protocol includes a novel technique of sharing the same physical channel for all transaction types. Two channels, the Transaction Attribute Channel (TAC) and the Transaction Data Channel (TDC) are used. The attribute channel transmits bus transaction attribute information optionally including a transaction type signal, a transaction ID, a valid signal, a bus agent ID signal, an address signal, a transaction size signal, a credit spend signal and a credit return signal. The data channel connected a data subset of the signal lines of the bus separate from the attribute subset of signal lines the bus. The data channel optionally transmits a data valid signal, a transaction ID signal, a bus agent ID signal and a last data signal to mark the last data of a current bus transaction.

    Abstract translation: 多核总线架构（MBA）协议包括一种为所有事务类型共享相同物理通道的新技术。 使用两个通道，交易属性通道（TAC）和交易数据通道（TDC）。 属性信道发送可选地包括交易类型信号，交易ID，有效信号，总线代理ID信号，地址信号，交易大小信号，信用支出信号和信用回报信号的总线交易属性信息。 数据通道连接总线信号线的数据子集，与总线信号线的属性子集分开。 数据信道可选地发送数据有效信号，事务ID信号，总线代理ID信号和最后数据信号，以标记当前总线事务的最后数据。

    Multi processor bridge with mixed Endian mode support
    85.
    发明授权
    Multi processor bridge with mixed Endian mode support 有权
    具有混合端模式支持的多处理器桥

    公开(公告)号：US09304954B2

    公开(公告)日：2016-04-05

    申请号：US14031567

    申请日：2013-09-19

    Applicant: Texas Instruments Incorporated

    Inventor： Daniel B Wu ,  Matthew D Pierson ,  Kai Chirca

    IPC: G06F12/00 ,  G06F13/16 ,  G06F13/40 ,  G06F12/08

    CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

    Abstract: An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The asynchronous bridge is aware of the endian view used by each individual processor within the attached subsystem, and can perform the appropriate endian conversion on each processor's transactions to adapt the transaction to/from the endian view used by the interconnect.

    Abstract translation: 在高速缓存一致主机和相干系统互连之间实现异步双域网桥。 该桥具有两个半部分，每个时钟/电源下降域主和互连中一个。 异步网桥了解连接子系统内每个处理器使用的端点视图，并且可以对每个处理器的事务执行适当的端序转换，以使交易与互连使用的端点视图相适应。

    FLEXIBLE ARBITRATION SCHEME FOR MULTI ENDPOINT ATOMIC ACCESSES IN MULTICORE SYSTEMS
    86.
    发明申请
    FLEXIBLE ARBITRATION SCHEME FOR MULTI ENDPOINT ATOMIC ACCESSES IN MULTICORE SYSTEMS 审中-公开
    用于多系统中多端点原子访问的灵活仲裁方案

    公开(公告)号：US20160062887A1

    公开(公告)日：2016-03-03

    申请号：US14937945

    申请日：2015-11-11

    Applicant: Texas Instruments Incorporated

    Inventor： Kai Chirca ,  Matthew D Pierson

    IPC: G06F12/08 ,  G06F3/06

    CPC classification number: G06F12/084 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0683 ,  G06F11/1064 ,  G06F13/1652 ,  G06F13/1668 ,  G06F2212/1016 ,  G06F2212/60

    Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace)in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. Two consecutive slots are assigned per cache line access to automatically guarantee the atomicity of all transactions within a single cache line. The need for synchronization among all the banks of a particular SRAM is eliminated, as synchronization is accomplished by assigning back to back slots.

    Abstract translation: 描述的MSMC（多核共享存储器控制器）是一种旨在管理多处理器内核，其他母盘外设或DMA之间流量的模块，以及多核SoC中的EMIF（外部存储器间隔）。 本发明在仲裁事务之前统一属于从属方的所有事务大小，以便降低仲裁过程的复杂性，并在所有主机之间提供最佳的带宽管理。 每个缓存行访问分配两个连续的插槽，以自动保证单个高速缓存行内所有事务的原子性。 消除了对特定SRAM的所有存储体之间同步的需要，因为通过分配背靠背槽来实现同步。

    OPTIMUM CACHE ACCESS SCHEME FOR MULTI ENDPOINT ATOMIC ACCESS IN A MULTICORE SYSTEM
    89.
    发明申请
    OPTIMUM CACHE ACCESS SCHEME FOR MULTI ENDPOINT ATOMIC ACCESS IN A MULTICORE SYSTEM 有权
    用于多重系统中多端点原子访问的最佳缓存访问方案

    公开(公告)号：US20140115265A1

    公开(公告)日：2014-04-24

    申请号：US14061494

    申请日：2013-10-23

    Applicant: Texas Instruments Incorporated

    Inventor： Kai Chirca ,  Matthew D. Pierson

    IPC: G06F12/08 ,  G06F13/16

    CPC classification number: G06F12/0815 ,  G06F12/0862 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/1684

    Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. The two consecutive slots assigned per cache line access are always in the same direction for maximum access rate.

    Abstract translation: 描述的MSMC（多核共享存储器控制器）是一种旨在管理多处理器内核，其他母盘外设或DMA之间流量的模块，以及多核SoC中的EMIF（外部存储器间隔）。 本发明在仲裁事务之前统一属于从属方的所有事务大小，以便降低仲裁过程的复杂性，并在所有主机之间提供最佳的带宽管理。 每个高速缓存行访问分配的两个连续插槽总是处于相同的方向，以获得最大访问速率。

    SYNCHRONIZING BARRIER SUPPORT WITH ZERO PERFORMANCE IMPACT
    90.
    发明申请
    SYNCHRONIZING BARRIER SUPPORT WITH ZERO PERFORMANCE IMPACT 有权
    与ZERO性能影响同步障碍物支持

    公开(公告)号：US20140115220A1

    公开(公告)日：2014-04-24

    申请号：US14056798

    申请日：2013-10-17

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Daniel B. Wu ,  Kai Chirca

    IPC: G06F13/40

    CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

    Abstract: The barrier-aware bridge tracks all outstanding transactions from the attached master. When a barrier transaction is sent from the master, it is tracked by the bridge, along with a snapshot of the current list of outstanding transactions, in a separate barrier tracking FIFO. Each barrier is separately tracked with whatever transactions that are outstanding at that time. As outstanding transaction responses are sent back to the master, their tracking information is simultaneously cleared from every barrier FIFO entry.

    Abstract translation: 障碍感知桥跟踪所附主机的所有未完成交易。 当从主机发送屏障事务时，它将在单独的屏障跟踪FIFO中由桥跟踪，以及当前未完成事务列表的快照。 每个屏障都被单独跟踪，当时任何未完成的交易。 由于未完成的交易响应被发送回主机，它们的跟踪信息将同时从每个障碍FIFO条目中清除。

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