公开(公告)号：US20090010070A1

公开(公告)日：2009-01-08

申请号：US12149422

申请日：2008-05-01

申请人： Takeshi Kajimoto ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Takashi Kono

发明人： Takeshi Kajimoto ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Takashi Kono

IPC分类号： G11C16/06 ,  G11C7/00

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/3459

摘要： In a flash memory, after an initial write operation ends, each bit line associated with a memory cell subjected to a write is precharged and each bit line associated with a memory cell that is not subjected to the write is discharged and verified to detect a memory cell low in threshold voltage and a memory cell thus detected is subjected to an additional write. The verification can be verified without being affected by a current flowing through the memory cell that is not subjected to the write. All memory cells can have their respective threshold voltages set accurately.

摘要翻译： 在闪速存储器中，在初始写入操作结束后，与经过写入的存储器单元相关联的每个位线被预充电，并且与不经过写入的存储器单元相关联的每个位线被放电并被验证以检测存储器 小区阈值电压和这样检测的存储单元经受附加写入。 可以验证验证，而不受流过不经过写入的存储器单元的电流的影响。 所有存储单元可以准确地设置其各自的阈值电压。

公开(公告)号：US20080285348A1

公开(公告)日：2008-11-20

申请号：US12153927

申请日：2008-05-28

申请人： Takashi Kono ,  Yuichi Kunori ,  Hironori Iga

发明人： Takashi Kono ,  Yuichi Kunori ,  Hironori Iga

IPC分类号： G11C16/24

CPC分类号： G11C16/0491 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/26

摘要： In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line in an upper layer via a switch is adopted, so that charge sharing write-in is carried out between two main bit lines. Accordingly, write-in of data into the flash memory can be carried out with low power consumption, and the threshold voltage can be controlled with precision.

公开(公告)号：US20080239826A1

公开(公告)日：2008-10-02

申请号：US12076787

申请日：2008-03-24

申请人： Tomoya Ogawa ,  Takashi Ito ,  Hidenori Mitani ,  Takashi Kono

发明人： Tomoya Ogawa ,  Takashi Ito ,  Hidenori Mitani ,  Takashi Kono

IPC分类号： G11C16/34

CPC分类号： G11C16/3404

摘要： When a data write sequence is started, initially, write data is latched in a data latch circuit corresponding to one memory mat. Then, a program pulse is applied to the memory mat, and data read from a memory cell, which is a data write target bit in the memory mat, is performed. Thereafter, verify determination of the memory mat is performed. After a verify operation for the memory mat is completed, a program pulse is applied to another memory mat, and a verify operation for another memory mat is performed.

摘要翻译： 当数据写入序列开始时，最初写入数据被锁存在对应于一个存储器垫的数据锁存电路中。 然后，将程序脉冲施加到存储器垫，并且执行从作为存储器垫中的数据写入目标位的存储单元读取的数据。 此后，验证是否执行存储垫的确定。 在存储器垫的验证操作完成之后，将程序脉冲施加到另一个存储器垫，并且执行另一存储器垫的验证操作。

公开(公告)号：US20070019478A1

公开(公告)日：2007-01-25

申请号：US11488621

申请日：2006-07-19

申请人： Takeshi Kajimoto ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Takashi Kono

发明人： Takeshi Kajimoto ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Takashi Kono

IPC分类号： G11C11/34 ,  G11C16/06 ,  G11C16/04

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/3459

摘要： In a flash memory, after an initial write operation ends, each bit line associated with a memory cell subjected to a write is precharged and each bit line associated with a memory cell that is not subjected to the write is discharged and verified to detect a memory cell low in threshold voltage and a memory cell thus detected is subjected to an additional write. The verification can be verified without being affected by a current flowing through the memory cell that is not subjected to the write. All memory cells can have their respective threshold voltages set accurately.

摘要翻译： 在闪速存储器中，在初始写入操作结束后，与经过写入的存储器单元相关联的每个位线被预充电，并且与不经过写入的存储器单元相关联的每个位线被放电并被验证以检测存储器 小区阈值电压和这样检测的存储单元经受附加写入。 可以验证验证，而不受流过不经过写入的存储器单元的电流的影响。 所有存储单元可以准确地设置其各自的阈值电压。

公开(公告)号：US20060270115A1

公开(公告)日：2006-11-30

申请号：US11492541

申请日：2006-07-25

申请人： Mitsunori Sano ,  Takashi Kono ,  Makoto Tsutsui

发明人： Mitsunori Sano ,  Takashi Kono ,  Makoto Tsutsui

IPC分类号： H01L21/00

CPC分类号： H01G9/012 ,  H01G9/042 ,  H01G9/10 ,  H01L2924/0002 ,  Y10S257/924 ,  Y10T29/417 ,  Y10T29/435 ,  Y10T29/4913 ,  H01L2924/00

摘要： In a chip type solid electrolytic capacitor including a capacitor element and a packaging resin covering the capacitor element, the packaging resin has a mount surface and a side surface adjacent to the mount surface. A terminal is electrically connected to the capacitor element and coupled to the packaging resin. The terminal extends along the mount surface and the side surface to have an outer surface exposed from the packaging resin and to have an inner surface opposite to the outer terminal surface. The inner surface has a stepwise shape formed by forging.

摘要翻译： 在包括电容器元件和覆盖电容器元件的封装树脂的芯片型固体电解电容器中，封装树脂具有与安装表面相邻的安装表面和侧表面。 端子电连接到电容器元件并且耦合到封装树脂。 端子沿着安装表面和侧表面延伸以具有从包装树脂露出的外表面并且具有与外端子表面相对的内表面。 内表面具有通过锻造形成的阶梯形状。

公开(公告)号：US07110282B2

公开(公告)日：2006-09-19

申请号：US10947213

申请日：2004-09-23

申请人： Takashi Kono ,  Takeshi Hamamoto

发明人： Takashi Kono ,  Takeshi Hamamoto

IPC分类号： G11C11/4063 ,  G11C11/4074 ,  G11C7/08 ,  G11C8/08 ,  G11C8/12 ,  G11C8/14 ,  H01L29/772

CPC分类号： G11C8/08 ,  G11C11/401 ,  G11C29/12 ,  G11C2029/1202

摘要： An insulated gate type field effect transistor in a memory cell array is a transistor having a gate insulating film which is thicker than a gate insulating film of an insulated gate type field effect transistor in an array peripheral circuit. DRAM (Dynamic Random Access Memory) cell-based semiconductor memory device can be implemented which allows a burn-in test to be accurately performed without degrading sensing operation characteristics even under a low power supply voltage.

摘要翻译： 存储单元阵列中的绝缘栅型场效应晶体管是具有比阵列外围电路中的绝缘栅型场效应晶体管的栅极绝缘膜厚的栅极绝缘膜的晶体管。 可以实现DRAM（动态随机存取存储器）基于单元的半导体存储器件，其即使在低电源电压下也能够精确地执行老化测试而不降低感测操作特性。

公开(公告)号：US06816422B2

公开(公告)日：2004-11-09

申请号：US10291776

申请日：2002-11-12

申请人： Kei Hamade ,  Takashi Kono ,  Kiyohiro Furutani

发明人： Kei Hamade ,  Takashi Kono ,  Kiyohiro Furutani

IPC分类号： G11C700

CPC分类号： G11C29/40 ,  G11C29/34 ,  G11C2029/0405 ,  G11C2029/2602

摘要： In a multi-bit test, an I/O combiner degenerates data of a plurality of bits read from a memory cell array to first to fourth data bus pairs in parallel and outputs the degenerated data to a fifth data bus. A read amplifier compares a logic level of the degenerated data received from the I/O combiner with a logic level of expected value data. If the logic level of the degenerated data coincides with the logic level of the expected value data, the read amplifier determines that data write and read to and from the plurality of bits have been normally performed. As a result, a semiconductor memory device can detect a word line defect in the multi-bit test.

摘要翻译： 在多位测试中，I / O组合器并行地将从存储单元阵列读取的多个位的数据退格为第一至第四数据总线对，并将退化的数据输出到第五数据总线。 读取放大器将从I / O组合器接收的退化数据的逻辑电平与期望值数据的逻辑电平进行比较。 如果退化数据的逻辑电平与期望值数据的逻辑电平一致，则读取放大器确定对多个位的数据写入和读取已经被正常地执行。 结果，半导体存储器件可以检测多位测试中的字线缺陷。

公开(公告)号：US06496441B2

公开(公告)日：2002-12-17

申请号：US09907743

申请日：2001-07-19

申请人： Takashi Kono ,  Tetsuo Kato

发明人： Takashi Kono ,  Tetsuo Kato

IPC分类号： G11C800

CPC分类号： G11C5/063 ,  G11C5/025 ,  G11C8/12

摘要： By devising the arrangement of memory arrays surrounding the central region of the chip, the total length of a data bus can be reduced. The memory arrays are arranged such that one of two memory arrays that are located at the positions point-symmetric with respect to the central region corresponds to lower DQ terminals, and the other memory array corresponds to upper DQ terminals. Preferably, the memory arrays corresponding to the upper DQ terminals and the memory arrays corresponding to the lower DQ terminals are each located collectively. Thus, a semiconductor memory device with improved data propagation characteristics on the data bus can be provided.

摘要翻译： 通过设计围绕芯片的中心区域的存储器阵列的布置，可以减少数据总线的总长度。 存储器阵列被布置成使得位于相对于中心区域点对称的位置的两个存储器阵列之一对应于较低的DQ端子，而另一个存储器阵列对应于上部DQ端子。 优选地，对应于上部DQ端子的存储器阵列和对应于下部DQ端子的存储器阵列各自集中地定位。 因此，可以提供在数据总线上具有改善的数据传播特性的半导体存储器件。

公开(公告)号：US06262931B1

公开(公告)日：2001-07-17

申请号：US09539893

申请日：2000-03-31

申请人： Takashi Kono ,  Kiyohiro Furutani ,  Takeshi Hamamoto ,  Katsuyoshi Mitsui

发明人： Takashi Kono ,  Kiyohiro Furutani ,  Takeshi Hamamoto ,  Katsuyoshi Mitsui

IPC分类号： G11C800

CPC分类号： G11C8/18 ,  G11C5/147

摘要： A control circuit & mode register outputs a signal responsive to each command to a VDC control circuit. The VDC control circuit outputs a signal PWRUP changing the quantity of a through current Ic of a comparator stored in a VDC in response to the command. The VDC control circuit internally generates a signal of which pulse width corresponds to a prescribed delay time, in response to input of the command. Therefore, activation of each bank may not be monitored but current consumption can be reduced by preferably controlling a power supply current while minimizing the number of delay circuits and wires.

摘要翻译： 控制电路和模式寄存器将响应于每个命令的信号输出到VDC控制电路。 VDC控制电路响应于该命令输出改变存储在VDC中的比较器的直流电流Ic的信号PWRUP。 VDC控制电路根据命令的输入内部产生脉冲宽度对应于规定的延迟时间的信号。 因此，通过优选地控制电源电流同时最小化延迟电路和电线的数量，可以不监视每个组的激活，而可以减少电流消耗。

公开(公告)号：US5847595A

公开(公告)日：1998-12-08

申请号：US757861

申请日：1996-11-27

申请人： Takashi Kono ,  Tsukasa Ooishi ,  Hideto Hidaka

发明人： Takashi Kono ,  Tsukasa Ooishi ,  Hideto Hidaka

IPC分类号： G01R31/28 ,  G06F11/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/413 ,  G11C29/00 ,  G11C29/12 ,  G11C29/14 ,  H03K3/01

CPC分类号： G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12005 ,  G11C29/48 ,  G01R31/31721

摘要： A semiconductor memory device includes a mode detection circuit for generating a mode detection signal in response to external input signals /RAS, /CAS and /WE, an internal potential generating circuit for generating and supplying to an output node an internal potential, in response to an activated potential control signal, and an internal potential control circuit for activating a potential control signal when a potential at the output node has not yet reached a predetermined potential in a case where mode detection signal indicates a mode other than the test mode, and for activating the potential control signal when the potential at the output node has not yet reached an externally supplied external reference potential in a case where the mode detection signal indicates the test mode. When external input signals are applied at a predetermined timing, a mode detection signal indicating the test mode is generated, and when the potential at the output node of the internal potential generating circuit has not yet reached the external reference potential, an internal potential is generated and supplied to the output node. Therefore, the internal potential can be controlled in accordance with the external reference potential.

摘要翻译： 半导体存储器件包括：模式检测电路，用于响应于外部输入信号/ RAS，/ CAS和/ WE生成模式检测信号;内部电位产生电路，用于响应于 激活电位控制信号和内部电位控制电路，用于在模式检测信号表示除了测试模式之外的模式的情况下当输出节点的电位尚未达到预定电位时激活电位控制信号，并且 在模式检测信号表示测试模式的情况下，当输出节点的电位尚未达到外部提供的外部参考电位时，激活电位控制信号。 当在预定定时施加外部输入信号时，产生指示测试模式的模式检测信号，并且当内部电位发生电路的输出节点处的电位尚未达到外部参考电位时，产生内部电位 并提供给输出节点。 因此，可以根据外部参考电位来控制内部电位。