公开(公告)号：US11823908B2

公开(公告)日：2023-11-21

申请号：US17549673

申请日：2021-12-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Yu Chen ,  Yu-Chi Lu ,  Chih-Pin Tsao ,  Shih-Hsun Chang

IPC: H01L21/28 ,  H01L29/49

CPC classification number: H01L21/28088 ,  H01L21/28185 ,  H01L29/4966

Abstract: A method includes removing a dummy gate to form a gate trench. A gate dielectric layer is deposited over a bottom and sidewalls of the gate trench. A first work function metal layer is deposited over the gate dielectric layer. A dummy layer is deposited over the first work function metal layer. An impurity is introduced into the dummy layer and the first work function metal layer after the dummy layer is deposited. The dummy layer is removed after the impurity is introduced into the dummy layer and the first work function metal layer. The gate trench is filled with a conductive material after the dummy layer is removed.

公开(公告)号：US11502050B2

公开(公告)日：2022-11-15

申请号：US17170624

申请日：2021-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Sheng-Wei Yeh ,  Yen-Yu Chen ,  Wen-Hao Cheng ,  Chih-Wei Lin ,  Chun-Chih Lin

IPC: H01L21/02 ,  H01L23/532 ,  H01L23/525 ,  H01L23/00

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

公开(公告)号：US11437420B2

公开(公告)日：2022-09-06

申请号：US16733433

申请日：2020-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Chi Hung ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wei Chuang Wu ,  Yen-Yu Chen ,  Chih-Kuan Yu

IPC: H01L27/146

Abstract: Some embodiments are directed towards an image sensor device. A photodetector is disposed in a semiconductor substrate, and a transfer transistor is disposed over photodetector. The transfer transistor includes a transfer gate having a lateral portion extending over a frontside of the semiconductor substrate and a vertical portion extending to a first depth below the frontside of the semiconductor substrate. A gate dielectric separates the lateral portion and the vertical portion from the semiconductor substrate. A backside trench isolation structure extends from a backside of the semiconductor substrate to a second depth below the frontside of the semiconductor substrate. The backside trench isolation structure laterally surrounds the photodetector, and the second depth is less than the first depth such that a lowermost portion of the vertical portion of the transfer transistor has a vertical overlap with an uppermost portion of the backside trench isolation structure.

公开(公告)号：US20220081759A1

公开(公告)日：2022-03-17

申请号：US17190761

申请日：2021-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Yu Lee ,  Yen-Yu Chen

IPC: C23C16/02 ,  H01L29/40 ,  H01L21/02 ,  H01J37/32 ,  C23C14/02 ,  C23C14/14 ,  C23C14/56 ,  C23C14/58 ,  C23C16/06 ,  C23C16/56

Abstract: Semiconductor processing apparatuses and methods are provided in which a pre-clean chamber receives a semiconductor wafer from a metal gate layer deposition chamber and at least partially removes an oxide layer on a metal gate layer. In some embodiments, a semiconductor processing apparatus includes a plurality of metal gate layer deposition chambers. Each of the metal gate layer deposition chambers is configured to form a metal gate layer on a semiconductor wafer. At least one pre-clean chamber of the apparatus is configured to receive the semiconductor wafer from one of the metal gate layer deposition chamber and at least partially remove an oxide layer on the metal gate layer.

公开(公告)号：US20210118700A1

公开(公告)日：2021-04-22

申请号：US16657841

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsuan-Chih Chu ,  Wen-Hao Cheng ,  Yen-Yu Chen ,  Yi-Ming Dai

IPC: H01L21/673 ,  H01L21/67 ,  H01L21/687 ,  H01L21/66

Abstract: The present disclosure provides a flexible workpiece pedestal capable of tilting a workpiece support surface. The workpiece pedestal further includes a heater mounted on the workpiece support surface. The heater includes a plurality of heating sources such as heating coils. The plurality of heating sources in the heater allows heating the workpiece at different temperatures for different zones of the workpiece. For example, the workpiece can have a central zone heated by a first heating coil, a first outer ring zone that is outside of the central zone heated by a second heating coil, a second outer ring zone that is outside of the first outer ring zone heated by a third heating coil. By using the tunable heating feature and the tilting feature of the workpiece pedestal, the present disclosure can reduce or eliminate the shadowing effect problem of the related workpiece pedestal in the art.

公开(公告)号：US20210071295A1

公开(公告)日：2021-03-11

申请号：US17101586

申请日：2020-11-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsuan-Chih Chu ,  Chien-Hsun Pan ,  Yen-Yu Chen ,  Chun-Chih Lin

IPC: C23C14/54 ,  H01L21/285 ,  C23C14/35 ,  C23C14/34 ,  H01L21/67 ,  H01J37/34

Abstract: Sputtering systems and methods are provided. In an embodiment, a sputtering system includes a chamber configured to receive a substrate, a sputtering target positioned within the chamber, and an electromagnet array over the sputtering target. The electromagnet array includes a plurality of electromagnets.

公开(公告)号：US20190259855A1

公开(公告)日：2019-08-22

申请号：US15898706

申请日：2018-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Yen-Yu Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L21/285 ,  H01L21/768 ,  H01L21/762

Abstract: A semiconductor device includes an active region over a substrate; a first cobalt-containing feature disposed over the active region; a conductive cap disposed over and in physical contact with the first cobalt-containing feature; and a second cobalt-containing feature disposed over and in physical contact with the conductive cap.

公开(公告)号：US10166650B2

公开(公告)日：2019-01-01

申请号：US15221187

申请日：2016-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang Cheng ,  Yen-Yu Chen ,  Chang-Sheng Lee ,  Wei Zhang

IPC: B24B37/00 ,  B24B37/013 ,  H01L21/66 ,  H01L21/67 ,  H01L21/306 ,  H01L21/3105 ,  B24B49/12 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

Abstract: A chemical-mechanical planarization (CMP) system includes a platen, a pad, a polish head, a rotating mechanism, a light source, and a detector. The pad is disposed on the platen. The polish head is configured to hold a wafer against the pad. The rotating mechanism is configured to rotate at least one of the platen and the polish head. The light source is configured to provide incident light to an end-point layer on the wafer. The detector is configured to detect absorption of the incident light by the end-point layer.

公开(公告)号：US09892982B2

公开(公告)日：2018-02-13

申请号：US14146996

申请日：2014-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Shu Tseng ,  Chien-Hua Chen ,  You-Feng Chen ,  Yen-Yu Chen ,  Zhong-Yi Chen ,  Yung-Haw Liaw

IPC: H01L21/027 ,  H01L21/66 ,  H01L21/67

CPC classification number: H01L22/26 ,  H01L21/0276 ,  H01L21/67017 ,  H01L21/67253

Abstract: Embodiments of mechanisms for processing a wafer are provided. A method for processing a wafer includes placing the wafer into a processing assembly and heating the wafer. The method also includes producing an exhaust flow from the processing assembly via a fluid-conduit assembly. The method further includes detecting an exhaust pressure of the exhaust flow in the fluid-conduit assembly and producing a first signal and a second signal corresponding to the exhaust pressure. In addition, the method includes regulating the exhaust flow in response to the first signal and controlling the processing assembly in response to the second signal.

公开(公告)号：US09553160B2

公开(公告)日：2017-01-24

申请号：US14049657

申请日：2013-10-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Jen Chen ,  Yen-Yu Chen ,  Chang-Sheng Lee ,  Wei Zhang

IPC: H01L21/66 ,  G01R31/26 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L29/4966 ,  H01L21/28194 ,  H01L22/12 ,  H01L22/20 ,  H01L29/513 ,  H01L29/517

Abstract: Embodiments of mechanisms of monitoring metal impurity in a high-k dielectric film are provided. The method includes forming an interfacial layer over a substrate. The method also includes forming a high-k dielectric film on the interfacial layer, and the interfacial layer and the high-k dielectric film form a stacked structure over the substrate. The method further includes conducting the first thickness measurement on the stacked structure. In addition, the method includes performing a treatment to the stacked structure after the first thickness measurement, and the treatment includes an annealing process. The method also includes conducting the second thickness measurement on the stacked structure after the treatment.

Abstract translation: 提供了在高k电介质膜中监测金属杂质的机理的实施例。 该方法包括在衬底上形成界面层。 该方法还包括在界面层上形成高k电介质膜，并且界面层和高k电介质膜在衬底上形成堆叠结构。 该方法还包括对堆叠结构进行第一厚度测量。 此外，该方法包括在第一厚度测量之后对堆叠结构进行处理，并且处理包括退火处理。 该方法还包括在处理之后对堆叠结构进行第二厚度测量。