公开(公告)号：US20160181266A1

公开(公告)日：2016-06-23

申请号：US14573208

申请日：2014-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/115 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/32139 ,  H01L21/32155 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11541 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7883

Abstract: An embedded flash memory device is provided. A gate stack includes a control gate arranged over a floating gate. An erase gate is arranged adjacent to a first side of the gate stack. A word line is arranged adjacent to a second side of the gate stack that is opposite the first side. The word line includes a word line ledge exhibiting a reduced height relative to a top surface of the word line and on an opposite side of the word line as the gate stack. A polysilicon logic gate has a top surface approximately even with the word line ledge. An ILD layer is arranged over the gate stack, the erase gate, the polysilicon logic gate, and the word lines. A contact extends through the ILD layer. A method of manufacturing the embedded flash memory device is also provided.

Abstract translation: 提供了一种嵌入式闪存设备。 栅极堆叠包括布置在浮动栅极上的控制栅极。 擦除栅极邻近栅堆叠的第一侧布置。 字线布置成与栅堆叠的与第一侧相对的第二侧相邻。 字线包括字线凸出部，该字线突出部相对于字线的顶表面减小高度，并且与字线堆叠在字线的相反侧。 多晶硅逻辑门具有大致均匀的字线凸缘的顶表面。 ILD层布置在栅极堆叠，擦除栅极，多晶硅逻辑门和字线之上。 一个触点延伸穿过ILD层。 还提供了一种制造嵌入式闪存设备的方法。

公开(公告)号：US20160181261A1

公开(公告)日：2016-06-23

申请号：US14580505

申请日：2014-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Harry-Hak-Lay Chuang ,  Shih-Chang Liu

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/76229 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11548

Abstract: The present disclosure relates a method of forming an integrated circuit. In some embodiments, the method is performed by patterning a first masking layer over a substrate to have a first plurality of openings at a memory cell region and a second plurality of openings at a boundary region. A first plurality of dielectric bodies are formed within the first plurality of openings and a second plurality of dielectric bodies are formed within the second plurality of openings. A second masking layer is formed over the first masking layer and the first and second plurality of dielectric bodies. The first and second masking layers are removed at the memory cell region, and a first conductive layer is formed to fill recesses between the first plurality of dielectric bodies. A planarization process reduces a height of the first conductive layer and removes the first conductive layer from over the boundary region.

Abstract translation: 本公开涉及一种形成集成电路的方法。 在一些实施例中，该方法通过在衬底上图案化第一掩模层来进行，以在存储单元区域处具有第一多个开口，并在边界区域具有第二多个开口。 在所述第一多个开口内形成有第一多个介电体，并且在所述第二多个开口内形成第二多个介电体。 在第一掩蔽层和第一和第二多个电介质体之上形成第二掩模层。 在存储单元区域处去除第一和第二掩模层，并且形成第一导电层以填充第一多个电介质体之间的凹部。 平坦化处理降低了第一导电层的高度，并从边界区域上移除第一导电层。

公开(公告)号：US09356142B2

公开(公告)日：2016-05-31

申请号：US14310277

申请日：2014-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsing Chang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/792 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/0847 ,  H01L29/42344 ,  H01L29/66484 ,  H01L29/66833 ,  H01L29/7831 ,  H01L29/792

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a first source/drain region and a second source/drain region. The first and second source/drain regions form a channel region therebetween. The semiconductor structure further includes a select gate and a memory gate spaced between the first and second source/drain regions over the channel region. The select gate extends over the channel region and terminates at a line end having a top surface asymmetric about an axis that extends along a length of the select gate and that bisects a width of the select gate. Even more, the semiconductor structure includes a charge trapping dielectric arranged between neighboring sidewalls of the memory gate and the select gate, and arranged under the memory gate. A method of manufacturing the semiconductor structure is also provided.

Abstract translation: 提供了分离栅闪存单元的半导体结构。 半导体结构包括包括第一源极/漏极区域和第二源极/漏极区域的半导体衬底。 第一和第二源极/漏极区域之间形成沟道区域。 半导体结构还包括选择栅极和在沟道区域上的第一和第二源极/漏极区域间隔开的存储栅极。 选择栅极延伸在沟道区上方并且终止于具有沿着沿着选择栅极的长度延伸的轴线的不对称的顶表面的线端，并且平分选择栅极的宽度。 更重要的是，半导体结构包括布置在存储器栅极和选择栅极的相邻侧壁之间并且布置在存储器栅极下方的电荷捕获电介质。 还提供了制造半导体结构的方法。

公开(公告)号：US20160086965A1

公开(公告)日：2016-03-24

申请号：US14493568

申请日：2014-09-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsueh Yang ,  Chung-Chiang Min ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/115

CPC classification number: H01L29/42344 ,  H01L27/1157 ,  H01L29/792

Abstract: The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has cuboid shaped memory gate and select gate covered upper surfaces by some spacers. Thus the memory gate and select gate are protected from silicide. The memory gate and select gate are defined self-aligned by the said spacers. The memory gate and select gate are formed by etching back corresponding conductive materials not covered by the spacers instead of recess processes. Thus the memory gate and select gate have planar upper surfaces and are well defined. The disclosed device and method is also capable of further scaling since photolithography processes are reduced.

Abstract translation: 本公开涉及自对准分离门存储器单元及其相关方法。 自对准分离栅极存储单元具有立方形形状的存储栅极，并且通过一些间隔物选择栅极覆盖的上表面。 因此，存储器栅极和选择栅极被保护以防止硅化物。 存储器栅极和选择栅极被所述间隔物自对准地限定。 存储栅极和选择栅极通过蚀刻不被间隔物覆盖的相应导电材料而不是凹陷工艺而形成。 因此，存储器栅极和选择栅极具有平坦的上表面并且被明确定义。 所公开的装置和方法还能够进一步缩放，因为光刻工艺被减少。

公开(公告)号：US09287279B2

公开(公告)日：2016-03-15

申请号：US14225874

申请日：2014-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsing Chang ,  Chang-Ming Wu ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Wei Cheng Wu ,  Harry-Hak-Lay Chuang

IPC: H01L27/115 ,  H01L29/788 ,  H01L21/28

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7883

Abstract: Some embodiments relate to a memory cell with a charge-trapping layer of nanocrystals, comprising a tunneling oxide layer along a select gate, a control oxide layer formed between a control gate and the tunnel oxide layer, and a plurality of nanocrystals arranged between the tunneling and control oxide layers. An encapsulating layer isolates the nanocrystals from the control oxide layer. Contact formation to the select gate includes a two-step etch. A first etch includes a selectivity between oxide and the encapsulating layer, and etches away the control oxide layer while leaving the encapsulating layer intact. A second etch, which has an opposite selectivity of the first etch, then etches away the encapsulating layer while leaving the tunneling oxide layer intact. As a result, the control oxide layer and nanocrystals are etched away from a surface of the select gate, while leaving the tunneling oxide layer intact for contact isolation.

Abstract translation: 一些实施例涉及具有纳米晶体的电荷捕获层的存储器单元，其包括沿着选择栅极的隧穿氧化物层，形成在控制栅极和隧道氧化物层之间的控制氧化物层，以及多个纳米晶体，其布置在隧道 并控制氧化物层。 封装层将纳米晶体与控制氧化物层隔离。 与选择栅极的接触形成包括两步蚀刻。 第一蚀刻包括氧化物和封装层之间的选择性，并且蚀刻掉控制氧化物层，同时保持封装层完好无损。 具有与第一蚀刻相反的选择性的第二蚀刻然后在完全留下隧道氧化物层的同时蚀刻封装层。 结果，将控制氧化物层和纳米晶体从选择栅极的表面蚀刻掉，同时使隧道氧化物层完好无损以进行接触隔离。

公开(公告)号：US20150364558A1

公开(公告)日：2015-12-17

申请号：US14306726

申请日：2014-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/115 ,  H01L29/788 ,  H01L21/28

CPC classification number: H01L29/42368 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/41725 ,  H01L29/42328 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7883 ,  H01L2924/1438

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a source region and a drain region. Further, the semiconductor structure includes a floating gate, a word line, and an erase gate located over the semiconductor substrate between the source and drain regions. The floating gate is arranged between the word line and the erase gate. Even more, the semiconductor structure includes a dielectric disposed between the erase and floating gates. A thickness of the dielectric between the erase and floating gates is variable and increases towards the semiconductor substrate. A method of manufacturing the semiconductor structure is also provided.

Abstract translation: 提供了分离栅闪存单元的半导体结构。 半导体结构包括包括源极区和漏极区的半导体衬底。 此外，半导体结构包括位于源极和漏极区域之间的半导体衬底上方的浮置栅极，字线和擦除栅极。 浮栅位于字线与擦除栅之间。 更进一步地，半导体结构包括设置在擦除栅极和浮栅之间的电介质。 擦除栅极和浮置栅极之间的电介质的厚度是可变的并朝向半导体衬底增加。 还提供了制造半导体结构的方法。

公开(公告)号：US12043537B2

公开(公告)日：2024-07-23

申请号：US16990106

申请日：2020-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Lin ,  Chang-Ming Wu ,  Ting-Jung Chen

IPC: H04R31/00 ,  B81B1/00 ,  B81B3/00 ,  B81C1/00

CPC classification number: B81B3/001 ,  B81B1/004 ,  B81B3/0021 ,  B81C1/00158 ,  B81C1/00531 ,  B81C1/00571 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2203/053

Abstract: The present disclosure provides a method of manufacturing a MEMS device. In some embodiments, a first interlayer dielectric layer is formed over a substrate, and a diaphragm is formed over the first interlayer dielectric layer. Then, a second interlayer dielectric layer is formed over the diaphragm. A first etch is performed to form an opening through the second interlayer dielectric layer and the diaphragm and reaching into an upper portion of the first interlayer dielectric layer. A second etch is performed to the first interlayer dielectric layer and the second interlayer dielectric layer to form recesses above and below the diaphragm and to respectively expose a portion of a top surface and a portion of a bottom surface of the diaphragm. A sidewall stopper is formed along a sidewall of the diaphragm into the recesses of the first interlayer dielectric layer and the second interlayer dielectric layer.

公开(公告)号：US11710622B2

公开(公告)日：2023-07-25

申请号：US17011268

申请日：2020-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Liao ,  Chang-Ming Wu ,  Lee-Chuan Tseng

IPC: H01L21/02 ,  H01L21/3065 ,  H01J37/32 ,  H01L21/3213 ,  C23C16/44 ,  H01L21/683

CPC classification number: H01J37/32862 ,  C23C16/4405 ,  H01J37/3244 ,  H01L21/02271 ,  H01L21/3065 ,  H01L21/32136 ,  H01J2237/334 ,  H01J2237/335 ,  H01L21/6831

Abstract: In some embodiments, a method for cleaning a processing chamber is provided. The method may be performed by introducing a processing gas into a processing chamber that has a by-product disposed along sidewalls of the processing chamber. A plasma is generated from the processing gas using a radio frequency signal. A lower electrode is connected to a first electric potential. Concurrently, a bias voltage having a second electric potential is applied to a sidewall electrode to induce ion bombardment of the by-product, in which the second electric potential has a larger magnitude than the first electric potential. The processing gas is evacuated from the processing chamber.

公开(公告)号：US20220285382A1

公开(公告)日：2022-09-08

申请号：US17826503

申请日：2022-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L27/11568 ,  H01L29/792 ,  H01L29/423 ,  H01L21/311 ,  H01L29/66

Abstract: A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

公开(公告)号：US11261083B2

公开(公告)日：2022-03-01

申请号：US16732442

申请日：2020-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lee-Chuan Tseng ,  Chang-Ming Wu

IPC: B81C1/00 ,  B81B7/02 ,  B81B3/00 ,  H01L21/768 ,  B81B7/00 ,  B81C3/00 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

Abstract: The present disclosure relates to a microelectromechanical systems (MEMS) package featuring a flat plate having a raised edge around its perimeter serving as an anti-stiction device, and an associated method of formation. A CMOS IC is provided having a dielectric structure surrounding a plurality of conductive interconnect layers disposed over a CMOS substrate. A MEMS IC is bonded to the dielectric structure such that it forms a cavity with a lowered central portion the dielectric structure, and the MEMS IC includes a movable mass that is arranged within the cavity. The CMOS IC includes an anti-stiction plate disposed under the movable mass. The anti-stiction plate is made of a conductive material and has a raised edge surrounding at least a part of a perimeter of a substantially planar upper surface.