公开(公告)号：US12165929B2

公开(公告)日：2024-12-10

申请号：US17876083

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Han Chen ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L27/092 ,  H01L29/08 ,  H01L29/165 ,  H01L29/267 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: In an embodiment, a device includes: a semiconductor substrate; a first fin extending from the semiconductor substrate; a second fin extending from the semiconductor substrate; an epitaxial source/drain region including: a main layer in the first fin and the second fin, the main layer including a first semiconductor material, the main layer having an upper faceted surface and a lower faceted surface, the upper faceted surface and the lower faceted surface each being raised from respective surfaces of the first fin and the second fin; and a semiconductor contact etch stop layer (CESL) contacting the upper faceted surface and the lower faceted surface of the main layer, the semiconductor CESL including a second semiconductor material, the second semiconductor material being different from the first semiconductor material.

公开(公告)号：US20240379459A1

公开(公告)日：2024-11-14

申请号：US18783030

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Han Chen ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L27/092 ,  H01L29/08 ,  H01L29/165 ,  H01L29/267 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: In an embodiment, a device includes: a semiconductor substrate; a first fin extending from the semiconductor substrate; a second fin extending from the semiconductor substrate; an epitaxial source/drain region including: a main layer in the first fin and the second fin, the main layer including a first semiconductor material, the main layer having an upper faceted surface and a lower faceted surface, the upper faceted surface and the lower faceted surface each being raised from respective surfaces of the first fin and the second fin; and a semiconductor contact etch stop layer (CESL) contacting the upper faceted surface and the lower faceted surface of the main layer, the semiconductor CESL including a second semiconductor material, the second semiconductor material being different from the first semiconductor material.

公开(公告)号：US12119378B2

公开(公告)日：2024-10-15

申请号：US17121073

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Heng Wang ,  I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/225 ,  H01L21/268 ,  H01L21/311 ,  H01L29/08 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02236 ,  H01L21/2253 ,  H01L21/268 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/785

Abstract: A semiconductor structure includes semiconductor fins disposed over a substrate, an epitaxial source/drain (S/D) feature disposed over the semiconductor fins, where a top surface portion of the epitaxial S/D feature includes two surfaces slanted downward toward each other at an angle, a silicide layer disposed conformally over the top portion of the epitaxial S/D feature, and an S/D contact disposed over the silicide layer, where a bottom portion of the S/D contact extends into the epitaxial S/D feature.

公开(公告)号：US20240297236A1

公开(公告)日：2024-09-05

申请号：US18648069

申请日：2024-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Han Chen ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/511 ,  H01L21/02271 ,  H01L21/31053 ,  H01L29/401 ,  H01L29/7851

Abstract: A semiconductor structure includes a fin protruding from a substrate, a first and a second metal gate stacks disposed over the fin, and a dielectric feature defining a sidewall of each of the first and the second metal gate stacks. Furthermore, the dielectric feature includes a two-layer structure, where sidewalls of the first layer are defined by the second layer, and where the first and the second layers have different compositions.

公开(公告)号：US12057488B2

公开(公告)日：2024-08-06

申请号：US17850393

申请日：2022-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Han Chen ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/511 ,  H01L21/02271 ,  H01L21/31053 ,  H01L29/401 ,  H01L29/7851

Abstract: A semiconductor structure includes a fin protruding from a substrate, a first and a second metal gate stacks disposed over the fin, and a dielectric feature defining a sidewall of each of the first and the second metal gate stacks. Furthermore, the dielectric feature includes a two-layer structure, where sidewalls of the first layer are defined by the second layer, and where the first and the second layers have different compositions.

公开(公告)号：US12051628B2

公开(公告)日：2024-07-30

申请号：US17977405

申请日：2022-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yu Yang ,  Yen-Ting Chen ,  Wei-Yang Lee ,  Fu-Kai Yang ,  Yen-Ming Chen

IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823468 ,  H01L21/0337 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823864 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate, at least two gate structures disposed over the substrate, each of the at least two gate structures including a gate electrode and a spacer disposed along sidewalls of the gate electrode, wherein the spacer includes a refill portion and a bottom portion, the refill portion of the spacer has a funnel shape such that a top surface of the refill portion of the spacer is larger than a bottom surface of the refill portion of the spacer, and a source/drain contact disposed over the substrate and between the spacers of the at least two gate structures.

公开(公告)号：US11968817B2

公开(公告)日：2024-04-23

申请号：US17682061

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Lin Chen ,  Chao-Yuan Chang ,  Ping-Wei Wang ,  Fu-Kai Yang ,  Ting Fang ,  I-Wen Wu ,  Shih-Hao Lin

IPC: H10B10/00 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40 ,  H01L29/417

CPC classification number: H10B10/12 ,  H01L21/02063 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L29/401 ,  H01L29/41791

Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.

公开(公告)号：US20240096999A1

公开(公告)日：2024-03-21

申请号：US18520326

申请日：2023-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Di Tzeng ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L29/45 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/785

Abstract: A device includes a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide; and a source/drain contact electrically connected to the source/drain region through the silicide. The silicide includes a conformal first portion in the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen.

公开(公告)号：US11855169B2

公开(公告)日：2023-12-26

申请号：US17826673

申请日：2022-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Di Tzeng ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L29/45 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40

CPC classification number: H01L29/45 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/785

Abstract: A device includes a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide; and a source/drain contact electrically connected to the source/drain region through the silicide. The silicide includes a conformal first portion in the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen.

公开(公告)号：US20230052380A1

公开(公告)日：2023-02-16

申请号：US17977405

申请日：2022-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yu Yang ,  Yen-Ting Chen ,  Wei-Yang Lee ,  Fu-Kai Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/033 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate, at least two gate structures disposed over the substrate, each of the at least two gate structures including a gate electrode and a spacer disposed along sidewalls of the gate electrode, wherein the spacer includes a refill portion and a bottom portion, the refill portion of the spacer has a funnel shape such that a top surface of the refill portion of the spacer is larger than a bottom surface of the refill portion of the spacer, and a source/drain contact disposed over the substrate and between the spacers of the at least two gate structures.