公开(公告)号：US5780332A

公开(公告)日：1998-07-14

申请号：US812973

申请日：1997-03-05

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L29/78 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10867 ,  H01L27/10832 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10873 ,  H01L27/10891

摘要： A semiconductor memory device includes a semiconductor substrate, an element isolation film formed on the substrate, element formation regions each defined in an island form in the surface of the substrate by the element isolation film, trenches formed in the element formation regions, respectively, capacitors each formed in a corresponding one of the trenches, each having a plate electrode formed of the substrate, a capacitor insulating film formed on the inner wall of the trench and a storage electrode filled in the trench with the capacitor insulating film disposed therebetween, transistors each formed in the element formation regions, and having a gate electrode which is formed to extend over the substrate and pass over the trench and the element formation region, a first impurity diffusion layer formed on one side of the gate electrode, a second impurity diffusion layer formed on the other side of the gate electrode, and channel regions formed on the element formation region on both sides of the trench below the gate electrode and respectively connected to the first and second impurity diffusion layers, connection electrodes for respectively connecting the storage electrodes to the first impurity diffusion layers, and signal transmission lines respectively connected to the second impurity diffusion layers.

摘要翻译： 半导体存储器件包括半导体衬底，形成在衬底上的元件隔离膜，通过元件隔离膜在衬底的表面中以岛状形成的元件形成区域，分别形成在元件形成区域中的沟槽，电容器 每个形成在对应的一个沟槽中，每个沟槽具有由衬底形成的平板电极，形成在沟槽的内壁上的电容器绝缘膜和填充在沟槽中的存储电极，其间设置有电容器绝缘膜，晶体管各自 形成在所述元件形成区域中，并且具有形成为在所述基板上延伸并越过所述沟槽和所述元件形成区域的栅电极，形成在所述栅电极的一侧上的第一杂质扩散层，第二杂质扩散层 形成在栅电极的另一侧上，以及形成在元件形成区上的沟道区 并且分别连接到第一和第二杂质扩散层，用于将存储电极分别连接到第一杂质扩散层的连接电极和分别连接到第二杂质扩散层的信号传输线。

公开(公告)号：US5627968A

公开(公告)日：1997-05-06

申请号：US274732

申请日：1994-07-18

申请人： Tohru Ozaki ,  Rikiya Okamoto ,  Junichi Sugiyama ,  Seiya Shimizu

发明人： Tohru Ozaki ,  Rikiya Okamoto ,  Junichi Sugiyama ,  Seiya Shimizu

IPC分类号： G06F15/16 ,  G06F13/16 ,  G06F13/38 ,  G06F13/362 ,  G06F13/36

CPC分类号： G06F13/1673

摘要： A data transfer apparatus which includes data devices which access a common, shared memory. Each data device is connected to a corresponding data buffer. A memory bus is connected to each of the data buffers and to the shared memory to allow data to be transferred between the data buffers and between the data devices and the shared memory via the data buffers. Data is transferrable between a transferring data device to a receiving data device by transferring data from the transferring data device to the data buffer corresponding to the transferring data device, from the data buffer corresponding to the transferring data device to the memory bus, from the memory bus to the data buffer corresponding to the receiving data device, and then from the data buffer corresponding to the receiving data device to the receiving data device. A data transfer controller controls the data buffers and the shared memory so that the shared memory does not transfer data onto the memory data bus when, during the transfer of data between the transferring data device and the receiving data device, data is being transferred between the data buffer corresponding to the transferring data device and the data buffer corresponding to the receiving data device via the memory bus.

摘要翻译： 一种数据传输装置，其包括访问公共共享存储器的数据装置。 每个数据设备连接到相应的数据缓冲区。 存储器总线连接到每个数据缓冲器和共享存储器，以允许数据通过数据缓冲器在数据缓冲器之间以及数据装置和共享存储器之间传送。 数据可以从传送数据设备传送到接收数据设备，通过从对应于传送数据设备的数据缓冲器传输数据到与传送数据设备对应的数据缓冲器，从对应于传送数据设备的数据缓冲器到存储器总线，从存储器 总线到对应于接收数据设备的数据缓冲器，然后从对应于接收数据设备的数据缓冲器传送到接收数据设备。 数据传输控制器控制数据缓冲器和共享存储器，使得在传送数据设备与接收数据设备之间的数据传输期间，数据正在传输数据之间，共享存储器不会将数据传送到存储器数据总线 通过存储器总线对应于传送数据装置和对应于接收数据装置的数据缓冲器的数据缓冲器。

公开(公告)号：US5578847A

公开(公告)日：1996-11-26

申请号：US402570

申请日：1995-03-13

申请人： Masami Aoki ,  Takashi Yamada ,  Hiroshi Takato ,  Tohru Ozaki ,  Katsuhiko Hieda ,  Akihiro Nitayama

发明人： Masami Aoki ,  Takashi Yamada ,  Hiroshi Takato ,  Tohru Ozaki ,  Katsuhiko Hieda ,  Akihiro Nitayama

IPC分类号： H01L21/822 ,  G11C11/401 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10817 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10882 ,  Y10S257/907

摘要： A plurality of bit line contacts provided on one bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL and a plurality of bit line contacts provided on an adjacent bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL which is different from the space in which a corresponding one of the bit line contacts formed on the former bit line is arranged.

摘要翻译： 设置在一个位线BL上的多个位线触点布置在每个设置在每个相邻的两个字线WL之间的每隔一个空间中，并且设置在相邻位线BL上的多个位线触点彼此布置 每个相邻的两个字线WL之间的空间不同于其中布置在前位线上形成的位线触点中的相应一个的空间。

公开(公告)号：US5519236A

公开(公告)日：1996-05-21

申请号：US266389

申请日：1994-06-27

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10864

摘要： A semiconductor memory device includes at least one memory cell formed on a substrate. The memory cell is constructed by a hole capacitor and a vertical transistor. The hole capacitor is formed in a hole on the substrate. The vertical transistor is formed in a semiconductor column formed in position adjacent to the hole.

摘要翻译： 半导体存储器件包括形成在衬底上的至少一个存储单元。 存储单元由空穴电容器和垂直晶体管构成。 孔电容器形成在基板上的孔中。 垂直晶体管形成在邻近孔的位置形成的半导体柱中。

公开(公告)号：US5488242A

公开(公告)日：1996-01-30

申请号：US156931

申请日：1993-11-24

申请人： Kazumasa Sunouchi ,  Hiroshi Takato ,  Tohru Ozaki ,  Naoko Okabe ,  Katsuhiko Hieda ,  Fumio Horiguchi ,  Akihiro Nitayama ,  Takashi Yamada ,  Kouji Hasimoto ,  Satosi Inoue

发明人： Kazumasa Sunouchi ,  Hiroshi Takato ,  Tohru Ozaki ,  Naoko Okabe ,  Katsuhiko Hieda ,  Fumio Horiguchi ,  Akihiro Nitayama ,  Takashi Yamada ,  Kouji Hasimoto ,  Satosi Inoue

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L27/02 ,  H01L29/68 ,  H01L29/92

CPC分类号： H01L27/10829

摘要： In a DRAM having a structure in which a storage node electrode is formed via an insulator film in a trench formed in a memory cell region to thereby form a capacitor, and in which the storage node electrode is connected in the source/drain regions of a MOSFET through a storage node contact formed in a part of the insulator film, the trench is disposed so as to deviate widthwise in a channel region of the MOSFET, so that the distance between adjacent element regions is reduced without causing misalignment of masks used in the formation of the storage node contact, thereby to provide a miniaturized high-reliability DRAM. In addition, the storage node contact and the trench can be formed in large size.

摘要翻译： 在具有通过形成在存储单元区域中的沟槽中的绝缘膜形成存储节点电极从而形成电容器的结构的DRAM中，并且其中存储节点电极连接在源极/漏极区域 MOSFET通过形成在绝缘膜的一部分中的存储节点接触，沟槽设置成在MOSFET的沟道区域中宽度偏离，使得相邻元件区域之间的距离减小，而不会导致在 形成存储节点接触，从而提供小型化的高可靠性DRAM。 此外，存储节点接触和沟槽可以形成为大尺寸。

公开(公告)号：US5414655A

公开(公告)日：1995-05-09

申请号：US94421

申请日：1993-07-16

申请人： Tohru Ozaki ,  Hiroshi Takato ,  Akihiko Nitayama

发明人： Tohru Ozaki ,  Hiroshi Takato ,  Akihiko Nitayama

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  G11C11/24

CPC分类号： H01L27/10808 ,  H01L27/105 ,  H01L2924/0002

摘要： A semiconductor device of this invention includes a semiconductor substrate, at least one memory cell section including a number of memory cells each formed of a capacitor and a MOS transistor formed on the semiconductor substrate, a peripheral circuit section formed on the semiconductor substrate in an area other than an area in which the memory cell section is formed, and a wiring layer serving as an upper electrode of the capacitor and serving as a wire of the peripheral circuit section.

摘要翻译： 本发明的半导体器件包括：半导体衬底;至少一个存储单元部分，包括由形成在半导体衬底上的电容器和MOS晶体管形成的多个存储单元，形成在半导体衬底上的区域中的外围电路部分 除了形成存储单元部分的区域之外，还具有用作电容器的上部电极并用作外围电路部分的布线的布线层。

公开(公告)号：US5365347A

公开(公告)日：1994-11-15

申请号：US824125

申请日：1992-01-22

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： G06T9/00 ,  H04N1/417 ,  H04N1/41

CPC分类号： H04N1/4175

摘要： In a coding apparatus, a first detecting device serves to detect a variation between conditions of pixels in a currently-coded line. A second detecting device serves to detect a variation between conditions of pixels in a reference line which immediately precedes the currently-coded line. A deciding device serves to decide a mode of MR coding in accordance with the variations detected by the first and second detecting devices. The first and second detecting devices and the deciding device are enabled to execute functions thereof in temporally parallel with each other.

摘要翻译： 在编码装置中，第一检测装置用于检测当前编码行中的像素的条件之间的变化。 第二检测装置用于检测紧接在当前编码行之前的参考线中的像素的条件之间的变化。 决定装置用于根据由第一和第二检测装置检测到的变化来确定MR编码的模式。 第一和第二检测装置和判定装置能够在时间上彼此平行地执行其功能。