公开(公告)号：US5500541A

公开(公告)日：1996-03-19

申请号：US343945

申请日：1994-11-17

申请人： Tomohide Terashima ,  Masanori Fukunaga

发明人： Tomohide Terashima ,  Masanori Fukunaga

IPC分类号： H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H03K5/153 ,  H05B41/282 ,  H01L29/861 ,  H01L31/107

CPC分类号： H01L27/0652 ,  H05B41/2828

摘要： A semiconductor device having a voltage sensing element is disclosed which allows reduction of power consumption in comparison with a conventional device and enables to obtain a sufficient output voltage to secure sensing accuracy even when an input voltage is small. In the voltage sensing element of the semiconductor device, an n.sup.- layer is formed on a front surface of a p.sup.- substrate. A p type diffused region and an n type diffused region are formed at a main surface of n.sup.- layer, spaced apart by a prescribed distance. An electrode is formed on p type diffused region, and an electrode is formed on n type diffused region. An electrode is formed on a rear surface of p.sup.- substrate. P.sup.- substrate and n.sup.- layer constitute a diode in a reversely biased state. As a result, power consumption is reduced in comparison with a conventional voltage dividing resistor circuit.

摘要翻译： 公开了一种具有电压感测元件的半导体器件，其与常规器件相比能够降低功耗，并且即使当输入电压较小时也能够获得足够的输出电压以确保感测精度。 在半导体器件的电压感测元件中，在p-衬底的前表面上形成n层。 p型扩散区域和n型扩散区域形成在n层的主表面上，间隔开规定的距离。 在p型扩散区域上形成电极，在n型扩散区域形成电极。 在p基板的后表面上形成电极。 P-衬底和n-层构成反向偏置状态的二极管。 结果，与传统的分压电阻电路相比，功耗降低。

公开(公告)号：US5497011A

公开(公告)日：1996-03-05

申请号：US459219

申请日：1995-06-02

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L27/06 ,  H01L21/8249 ,  H01L29/74 ,  H01L29/745 ,  H01L29/749

CPC分类号： H01L29/7436 ,  H01L29/7455 ,  H01L29/749

摘要： In this semiconductor device, first, fifth and fourth impurity regions of a second conductivity type are formed on a main surface of a semiconductor layer of a first conductivity type with a predetermined space between each other. Second and third impurity regions of the first conductivity type are formed on the main surface of the first impurity region with a predetermined space between each other. A second gate electrode is formed between the second and third impurity regions. A first gate electrode is formed between the third impurity region and the semiconductor layer. A cathode electrode is connected to the third impurity region, and a short-circuit electrode is connected to first and second impurity regions. The first and fifth impurity regions are electrically short-circuited. Thereby, in the on state of the thyristor operation, the transistor including the second gate electrode can be off, whereby an entire hole current in the semiconductor layer forms a base current of one of the bipolar transistors, resulting in reduction of the holding current. Since the second gate electrode is provided independently from the first gate electrode, the gate length of the second gate electrode can be reduced, so that the on-resistance can be reduced, and thus the maximum controllable current can be increased.

摘要翻译： 在该半导体器件中，第一导电类型的半导体层的主表面上形成有第二导电类型的第一和第五杂质区和第四杂质区之间的预定间隔。 第一导电类型的第二和第三杂质区形成在第一杂质区的主表面上彼此之间具有预定的空间。 第二栅电极形成在第二和第三杂质区之间。 在第三杂质区和半导体层之间形成第一栅电极。 阴极与第三杂质区连接，短路电极与第一和第二杂质区连接。 第一和第五杂质区域电短路。 因此，在晶闸管工作的导通状态下，包含第二栅电极的晶体管可以截止，由此半导体层中的整个空穴电流形成双极晶体管之一的基极电流，导致保持电流的降低。 由于第二栅电极独立于第一栅极设置，所以可以减小第二栅电极的栅极长度，从而可以降低导通电阻，从而可以提高最大可控电流。

公开(公告)号：US5485030A

公开(公告)日：1996-01-16

申请号：US371487

申请日：1995-01-11

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L21/331 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/73 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861 ,  H01L27/04

CPC分类号： H01L29/7824 ,  H01L29/0649 ,  H01L29/102 ,  H01L29/402 ,  H01L29/7394 ,  H01L29/7436 ,  H01L29/78603 ,  H01L29/8611 ,  H01L29/0692 ,  H01L29/0696 ,  Y10S438/981

摘要： A high-breakdown voltage semiconductor device and a fabrication method are disclosed. A dielectric layer dielectrically isolates a semiconductor substrate from an n.sup.- type semiconductor layer. An n.sup.+ type semiconductor region having a lower resistance than the n.sup.+ type semiconductor layer is formed as if surrounded by a p.sup.+ type semiconductor region. The dielectric layer consists of a relatively thick first region and a relatively thin second region. The n.sup.+ type semiconductor region, which is located above the first region, occupies a narrower area than the first region. Thus, by forming the dielectric layer thick immediately under the first semiconductor layer and controlling the thickness of the dielectric layer at other potions, the breakdown voltage of the semiconductor device is improved without curbing RESURF effect.

摘要翻译： 公开了一种高耐压半导体器件和制造方法。 介电层介电地将半导体衬底与n-型半导体层隔离。 像p +型半导体区域一样形成具有比n +型半导体层低的电阻的n +型半导体区域。 电介质层由相对较厚的第一区域和较薄的第二区域组成。 位于第一区域上方的n +型半导体区域占据比第一区域窄的区域。 因此，通过在第一半导体层的正下方形成电介质层，并且控制其它部分的电介质层的厚度，可以提高半导体器件的击穿电压，而不会抑制RESURF效应。

公开(公告)号：US5477064A

公开(公告)日：1995-12-19

申请号：US977169

申请日：1992-11-16

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L29/74 ,  H01L21/332 ,  H01L29/745 ,  H01L29/749 ,  H01L29/06 ,  H01L29/747

CPC分类号： H01L29/66378 ,  H01L29/7455

摘要： An object of the present invention is to provide a semiconductor device which is designed so as to increase a maximum controllable current and decrease hold current without degrading its characteristic and to provide a method of manufacturing such a semiconductor device. A transistor formation region 3 and a P diffusion region 15 are selectively formed through an insulating film 4 between gate electrodes 5 on an N.sup.- epitaxial layer 2. In a transistor formation region 3, an N.sup.+ diffusion region 12 is formed on a P diffusion region 11, a P diffusion region 13 is formed on the N.sup.+ diffusion region 12, and an N.sup.+ diffusion region 14 is selectively formed on a surface of the P diffusion region 13. Then, a cathode electrode 7 is formed on the P diffusion region 13, N.sup.+ diffusion region 14 and P diffusion region 15, and an anode electrode 8 is formed on a second major surface of the P.sup.+ substrate 1. Due to a structural characteristic that an increase in current between electrodes 7 and 8 causes no latch-up phenomenon, etc., a maximum controllable current can be increased, and hold current can be decreased.

摘要翻译： 本发明的目的是提供一种半导体器件，其被设计为增加最大可控电流并降低保持电流而不降低其特性，并提供制造这种半导体器件的方法。 通过N-外延层2上的栅电极5之间的绝缘膜4选择性地形成晶体管形成区域3和P扩散区域15.在晶体管形成区域3中，在P扩散区域上形成N +扩散区域12 如图11所示，在N +扩散区域12上形成P扩散区域13，在P扩散区域13的表面上选择性地形成N +扩散区域14.然后，在P扩散区域13上形成阴极电极7， N +扩散区域14和P扩散区域15，并且阳极电极8形成在P +衬底1的第二主表面上。由于电极7和8之间的电流增加不产生闩锁现象的结构特征， 可以增加最大可控电流，并且可以降低保持电流。

公开(公告)号：US5389801A

公开(公告)日：1995-02-14

申请号：US972290

申请日：1992-11-05

申请人： Tomohide Terashima ,  Gourab Majumdar

发明人： Tomohide Terashima ,  Gourab Majumdar

IPC分类号： H01L29/78 ,  H01L21/332 ,  H01L21/336 ,  H01L29/06 ,  H01L29/74 ,  H01L29/749 ,  H01L23/58 ,  H01L27/01 ,  H01L31/111

CPC分类号： H01L29/66378 ,  H01L29/0649 ,  H01L29/7455 ,  H01L29/749

摘要： A general object of the present invention is to make a maximum controllable current large without exerting adverse effect on other characteristics. In a surface of an n.sup.- layer 2 formed on a p.sup.+ substrate 1, p diffusion regions 3a, 3b and 3c are formed separated by n.sup.+ diffusion regions 4a, 4b and an oxidation film 9. Above the p diffusion regions 3b and 3c, gate electrodes 5a and 5b are formed insulated from the surrounding by an oxidation film 6. An Al-Si electrode 7 is in contact with the p diffusion region 3a and the n.sup.+ diffusion region 4a while a metal electrode 8 is in contact with the p.sup.+ substrate 1. By virtue of interposition of the oxidation film 9, a thyristor consisting of the n.sup.+ diffusion region 4a, p diffusion region 3a, n.sup.- layer 2 and p.sup.+ substrate 1 is prevented from being actuated.

摘要翻译： 本发明的一般目的是使最大可控电流大，而不会对其它特性产生不利影响。 在p +衬底1上形成的n层2的表面中，由n +扩散区域4a，4b和氧化膜9隔开形成p扩散区域3a，3b和3c。在p扩散区域3b和3c上方， 电极5a和5b通过氧化膜6与周围形成绝缘.Al-Si电极7与p扩散区域3a和n +扩散区域4a接触，而金属电极8与p +衬底1接触 通过插入氧化膜9，防止由n +扩散区域4a，p扩散区域3a，n-层2和p +衬底1组成的晶闸管被致动。

公开(公告)号：US5324670A

公开(公告)日：1994-06-28

申请号：US921684

申请日：1992-07-30

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L29/74 ,  H01L21/332 ,  H01L29/745 ,  H01L29/749 ,  H01L49/00

CPC分类号： H01L29/66378 ,  H01L29/7455

摘要： A thyristor structure comprises a p.sup.+ -type substrate (21), an n-type base layer (22), a first p-type diffusion region (23) and an n.sup.+ -type diffusion region (25). A MOS structure comprises the base layer (22), first and second p-type diffusion regions (23, 24) and the n.sup.+ -type diffusion region (25). A positive voltage is applied to a gate electrode (27) to form a channel in a portion of the first diffusion region (23) just under the gate electrode (27), so that a cathode electrode (28) supplies carriers to the base layer (22) through the n.sup.+ -type diffusion region (25) and the channel, to turn on the thyristor. A negative voltage is applied to the gate electrode (27) to form a channel in a portion of the base layer (22) just under the gate electrode (27), so that the first p-type diffusion region (23) and the n.sup.+ -type diffusion region (25) are shorted through the channel, the second p-type diffusion region (24) and the cathode electrode (28), to turn off the thyristor.

摘要翻译： 晶闸管结构包括p +型衬底（21），n型基极层（22），第一p型扩散区域（23）和n +型扩散区域（25）。 MOS结构包括基极层（22），第一和第二p型扩散区（23,24）和n +型扩散区（25）。 向栅电极（27）施加正电压，在栅极（27）正下方的第一扩散区域（23）的一部分形成沟道，使得阴极电极（28）向基底层 （22）通过n +型扩散区（25）和通道，导通晶闸管。 在栅电极（27）上施加负电压以在基极层（22）的正下方形成沟道，使得第一p型扩散区（23）和n + 型扩散区域（25）通过沟道，第二p型扩散区域（24）和阴极电极（28）短路，以关断晶闸管。

公开(公告)号：US5309002A

公开(公告)日：1994-05-03

申请号：US21462

申请日：1993-02-23

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L29/744 ,  H01L21/329 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78 ,  H01L29/00

CPC分类号： H01L29/66356 ,  H01L29/7391 ,  Y10S257/914

摘要： Between electrodes (9) and (10) are formed a p.sup.+ substrate (2), an n.sup.- epitaxial layer (1) having a protruding portion (3), an n.sup.+ diffusion region (4) and p.sup.+ diffusion regions (13). Control electrodes (6) are formed on insulating films (5) on opposite sides of the protruding portion (3) and n.sup.+ diffusion region (4). The potential at the control electrodes (6) is increased or decreased with the potential at an electrode (10) increased relative to an electrode (9) to generate potential barrier or conductivity modulation in the n.sup.- epitaxial layer (1), whereby a semiconductor device turns off or on. Introduced holes are drawn through the p.sup.+ diffusion regions (13) when the semiconductor device turns off, to provide a small resistance and a short distance when the holes are drawn without changes in the area of the n.sup.+ diffusion region (4). This permits the semiconductor device to have small switching loss and high switching speed with a low ON-voltage.

摘要翻译： 在电极（9）和（10）之间形成有p +衬底（2），具有突出部分（3），n +扩散区域（4）和p +扩散区域（13）的n-外延层（1）。 控制电极（6）形成在突出部（3）和n +扩散区（4）的相对侧的绝缘膜（5）上。 控制电极（6）上的电位随着电极（10）上的电位相对于电极（9）而增加或减小，以在n外延层（1）中产生势垒或电导率调制，由此半导体 设备关闭或打开。 当半导体器件关闭时，引入的空穴通过p +扩散区域（13）被拉出，以便在不改变n +扩散区域（4）的区域的情况下提供小的电阻和短的距离。 这允许半导体器件在低导通电压下具有小的开关损耗和高开关速度。

公开(公告)号：US5293056A

公开(公告)日：1994-03-08

申请号：US863758

申请日：1992-04-06

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L21/18 ,  H01L21/336 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/66734 ,  H01L29/0657 ,  H01L29/66712 ,  H01L29/7813 ,  H01L21/187 ,  H01L29/0638 ,  H01L29/4236 ,  Y10S148/05 ,  Y10S438/977

摘要： A semiconductor device includes an N.sup.- type semiconductor layer (2). The N.sup.- type semiconductor layer (2) includes a triangular pole trench (10), an apex portion thereof contains a gate electrode (5). The trench (10) penetrates the semiconductor layer (2) and a P type well region (3) and projects into an N.sup.+ type source region (4). A source electrode (7) is disposed so as to be insulated from the semiconductor layer (2) by an oxide film (9) and in contact with the well region (3) and the source region (4). A drain electrode (8) is connected to the semiconductor layer (2) through an N.sup.+ type semiconductor substrate (1). With a higher potential at the gate electrode (5) than at the source electrode (7), the well region (3) is partially inverted into N type near the trench (10). Thus, the semiconductor device is turned on due to a channel created associated to the conductivity type inversion. Most of current flow allowed in the semiconductor layer (2) by the channel flows near the trench (10). Hence, even when process patterns are refined, electrode-to-electrode insulation remains undegraded in the semiconductor device, attaining low on-resistance and high off-breakdown voltage.

摘要翻译： 半导体器件包括N型半导体层（2）。 N型半导体层（2）包括三角形极沟（10），其顶部包含栅电极（5）。 沟槽（10）穿透半导体层（2）和P型阱区（3）并投入到N +型源极区（4）中。 源电极（7）被设置为与氧化膜（9）与半导体层（2）绝缘并与阱区（3）和源极区（4）接触。 漏电极（8）通过N +型半导体衬底（1）与半导体层（2）连接。 在栅电极（5）处的电位高于源电极（7）时，阱区（3）在沟槽（10）附近被部分地倒置为N型。 因此，由于与导电类型反转相关联的通道而导致半导体器件导通。 通过沟槽在半导体层（2）中允许的大部分电流流过在沟槽（10）附近流动。 因此，即使在精加工图案的情况下，半导体装置中的电极对电极绝缘体仍然保持不劣化，从而获得低的导通电阻和高的截止击穿电压。

公开(公告)号：US5270568A

公开(公告)日：1993-12-14

申请号：US709988

申请日：1991-06-04

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L29/41 ,  H01L29/06 ,  H01L29/40 ,  H01L29/34

CPC分类号： H01L29/404 ,  H01L29/0619

摘要： Conductive plates (16a-16e), or floating semiconductor regions (17a-17d), or conductive plates (16a, 16c, 16e) and floating semiconductor regions (17a, 17d) are disposed in alignment so that a coupling capacitance between the conductive plates and/or the floating semiconductor regions which are adjacent to each other decrease as a distance from a first or second semiconductor region (12, 13) increases. Therefore, the respective potentials at the conductive plates or the floating semiconductor regions can be varied linearly (or at equal potential differences), and corresponding potential distribution can be achieved on the surface of a semiconductor substrate (11). As a result, electric field concentration on the surface of the semiconductor substrate (11) just under a high potential conductive layer (14) can be prevented effectively even by the use of an insulating layer (15) with a common thickness.

公开(公告)号：US5204545A

公开(公告)日：1993-04-20

申请号：US807754

申请日：1991-12-17

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L29/06 ,  H01L29/40

CPC分类号： H01L29/404

摘要： There is provided p diffusion regions (18a, 18b) in the surface of an end portion of the n island (7) formed on the p.sup.- substrate (12). The insulation film (14) is formed on the n island (7) to form therein conductive plates (16a-16e). The p diffusion regions (18a, 18b) and the conductive plates (16a-16e) are alternately arranged and so aligned that adjacent pairs of end portions thereof overlap with each other. Capacitances of capacitive coupling of the conductive plates (16a-16e) and the p diffusion regions (18a, 18b) are optimized so that potentials of the conductive plates (16a-16e) and the p diffusion regions (18a, 18b) can substantially linearly change from a low level to a high level. Thus, the concentration of electric field can be prevented.

摘要翻译： 在形成在p基板（12）上的n岛（7）的端部的表面中设置有p个扩散区（18a，18b）。 绝缘膜（14）形成在n岛（7）上，以形成导电板（16a-16e）。 p扩散区域（18a，18b）和导电板（16a-16e）交替地布置成使其相邻的一对端部彼此重叠。 优化导电板（16a-16e）和p扩散区（18a，18b）的电容耦合的电容，使得导电板（16a-16e）和p扩散区（18a，18b）的电位可以基本上线性 从低水平转变为高水平。 因此，能够防止电场的集中。