公开(公告)号：US5200638A

公开(公告)日：1993-04-06

申请号：US547243

申请日：1990-07-03

申请人： Takeshi Kida ,  Kazumasa Satsuma ,  Gourab Majumdar ,  Tomohide Terashima ,  Hiroshi Yamaguchi ,  Masanori Fukunaga ,  Masao Yoshizawa

发明人： Takeshi Kida ,  Kazumasa Satsuma ,  Gourab Majumdar ,  Tomohide Terashima ,  Hiroshi Yamaguchi ,  Masanori Fukunaga ,  Masao Yoshizawa

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/336 ,  H01L21/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/732 ,  H01L29/735 ,  H01L29/739 ,  H01L29/745 ,  H01L29/78 ,  H01L29/861

CPC分类号： H01L29/404 ,  H01L29/66681 ,  H01L29/735 ,  H01L29/7393 ,  H01L29/7455 ,  H01L29/7826 ,  H01L29/8611

摘要： On the p.sup.- substrate, the n.sup.- epitaxial layer is surrounded and isolated by the p well. In the surface of the n.sup.- epitaxial layer, there is provided the p floating region in the vicinity of the p well, on which the sense electrode is provided. The insulation film and the conductive film are formed on the n.sup.- epitaxial layer between the p well and the p floating region to overlap them. The conductive film and the p floating region serve as a composite field plate, which makes it hard that the surface electric field distribution is influenced by the state of electric charge in the surface and relieves the surface electric field by expanding the depletion layer, which extends from the pn junction between the n.sup.31 epitaxial layer and the p well into the n.sup.- epitaxial layer in current blocking state, toward the center of the n.sup.- epitaxial layer. The potential of the p floating region is determined by capacity coupling in the current blocking state and thus the sense voltage characteristics through the sense electrode can be smooth.

公开(公告)号：US5279977A

公开(公告)日：1994-01-18

申请号：US997924

申请日：1992-12-29

申请人： Takeshi Kida ,  Kazumasa Satsuma ,  Gourab Majumdar ,  Tomohide Terashima ,  Hiroshi Yamaguchi ,  Masanori Fukunaga ,  Masao Yoshizawa

发明人： Takeshi Kida ,  Kazumasa Satsuma ,  Gourab Majumdar ,  Tomohide Terashima ,  Hiroshi Yamaguchi ,  Masanori Fukunaga ,  Masao Yoshizawa

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/336 ,  H01L21/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/732 ,  H01L29/735 ,  H01L29/739 ,  H01L29/745 ,  H01L29/78 ,  H01L29/861 ,  H01L21/265

CPC分类号： H01L29/404 ,  H01L29/66681 ,  H01L29/735 ,  H01L29/7393 ,  H01L29/7455 ,  H01L29/7826 ,  H01L29/8611

摘要： On the p.sup.- substrate, the n.sup.- epitaxial layer is surrounded and isolated by the p well. In the surface of the n.sup.- epitaxial layer, there is provided the p floating region in the vicinity of the p well, on which the sense electrode is provided. The insulation film and the conductive film are formed on the n.sup.- epitaxial layer between the p well and the p floating region to overlap them. The conductive film and the p floating region serve as a composite field plate, which makes it hard that the surface electric field distribution is influenced by the state of electric charge in the surface and relieves the surface electric field by expanding the depletion layer, which extends from the pn junction between the n.sup.- epitaxial layer and the p well into the n.sup.- epitaxial layer in current blocking state, toward the center of the n.sup.- epitaxial layer. The potential of the p floating region is determined by capacity coupling in the current blocking state and thus the sense voltage characteristics through the sense electrode can be smooth.

摘要翻译： 在p-衬底上，n型外延层由p阱包围和隔离。 在n外延层的表面中，在p阱附近提供p浮置区，在其上设置感测电极。 绝缘膜和导电膜形成在p阱和p浮动区之间的n外延层上以重叠。 导电膜和p浮动区域用作复合场板，这使得表面电场分布受表面电荷状态的影响很困难，通过扩展耗尽层来减轻表面电场，延伸 从n-外延层和p阱之间的pn结到电流阻挡状态的n-外延层朝向n-外延层的中心。 p浮动区域的电位由电流阻塞状态下的电容耦合决定，因此通过感测电极的感测电压特性可以是平滑的。

公开(公告)号：US5258641A

公开(公告)日：1993-11-02

申请号：US944074

申请日：1992-09-11

申请人： Takeshi Kida ,  Kazumasa Satsuma ,  Gourab Majumdar ,  Tomohide Terashima ,  Hiroshi Yamaguchi ,  Masanori Fukunaga ,  Masao Yoshizawa

发明人： Takeshi Kida ,  Kazumasa Satsuma ,  Gourab Majumdar ,  Tomohide Terashima ,  Hiroshi Yamaguchi ,  Masanori Fukunaga ,  Masao Yoshizawa

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/735 ,  H01L29/739 ,  H01L29/745 ,  H01L29/78 ,  H01L29/861 ,  H01L29/68

CPC分类号： H01L29/404 ,  H01L29/66681 ,  H01L29/735 ,  H01L29/7393 ,  H01L29/7455 ,  H01L29/7826 ,  H01L29/8611

摘要： On the p.sup.- substrate, the n.sup.- epitaxial layer is surrounded and isolated by the p well. In the surface of the n.sup.- epitaxial layer, there is provided the p floating region in the vicinity of the p well, on which the sense electrode is provided. The insulation film and the conductive film are formed on the n.sup.- epitaxial layer between the p well and the p floating region to overlap them. The conductive film and the p floating region serve as a composite field plate, which makes it hard that the surface electric field distribution is influenced by the state of electric charge in the surface and relieves the surface electric field by expanding the depletion layer, which extends from the pn junction between the n.sup.- epitaxial layer and the p well into the n.sup.- epitaxial layer in current blocking state, toward the center of the n.sup.- epitaxial layer. The potential of the p floating region is determined by capacity coupling in the current blocking state and thus the sense voltage characteristics through the sense electrode can be smooth.

摘要翻译： 在p-衬底上，n型外延层由p阱包围和隔离。 在n外延层的表面中，在p阱附近提供p浮置区，在其上设置感测电极。 绝缘膜和导电膜形成在p阱和p浮动区之间的n外延层上以重叠。 导电膜和p浮动区域用作复合场板，这使得表面电场分布受表面电荷状态的影响很困难，通过扩展耗尽层来减轻表面电场，延伸 从n-外延层和p阱之间的pn结到电流阻挡状态的n-外延层朝向n-外延层的中心。 p浮动区域的电位由电流阻塞状态下的电容耦合决定，因此通过感测电极的感测电压特性可以是平滑的。

公开(公告)号：US5726598A

公开(公告)日：1998-03-10

申请号：US743567

申请日：1996-11-04

申请人： Tomohide Terashima ,  Masanori Fukunaga

发明人： Tomohide Terashima ,  Masanori Fukunaga

IPC分类号： H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H03K5/153 ,  H05B41/282

CPC分类号： H01L27/0652 ,  H05B41/2828

摘要： A semiconductor device having a voltage sensing element is disclosed which allows reduction of power consumption in comparison with a conventional device and enables to obtain a sufficient output voltage to secure sensing accuracy even when an input voltage is small. In the voltage sensing element of the semiconductor device, an n.sup.- layer is formed on a front surface of a p.sup.- substrate. A p type diffused region and an n type diffused region are formed at a main surface of n.sup.- layer, spaced apart by a prescribed distance. An electrode is formed on p type diffused region, and an electrode is formed on n type diffused region. An electrode is formed on a rear surface of p.sup.- substrate. P.sup.- substrate and n.sup.- layer constitute a diode in a reversely biased state. As a result, power consumption is reduced in comparison with a conventional voltage dividing resistor circuit.

公开(公告)号：US5500541A

公开(公告)日：1996-03-19

申请号：US343945

申请日：1994-11-17

申请人： Tomohide Terashima ,  Masanori Fukunaga

发明人： Tomohide Terashima ,  Masanori Fukunaga

IPC分类号： H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H03K5/153 ,  H05B41/282 ,  H01L29/861 ,  H01L31/107

CPC分类号： H01L27/0652 ,  H05B41/2828

摘要： A semiconductor device having a voltage sensing element is disclosed which allows reduction of power consumption in comparison with a conventional device and enables to obtain a sufficient output voltage to secure sensing accuracy even when an input voltage is small. In the voltage sensing element of the semiconductor device, an n.sup.- layer is formed on a front surface of a p.sup.- substrate. A p type diffused region and an n type diffused region are formed at a main surface of n.sup.- layer, spaced apart by a prescribed distance. An electrode is formed on p type diffused region, and an electrode is formed on n type diffused region. An electrode is formed on a rear surface of p.sup.- substrate. P.sup.- substrate and n.sup.- layer constitute a diode in a reversely biased state. As a result, power consumption is reduced in comparison with a conventional voltage dividing resistor circuit.

摘要翻译： 公开了一种具有电压感测元件的半导体器件，其与常规器件相比能够降低功耗，并且即使当输入电压较小时也能够获得足够的输出电压以确保感测精度。 在半导体器件的电压感测元件中，在p-衬底的前表面上形成n层。 p型扩散区域和n型扩散区域形成在n层的主表面上，间隔开规定的距离。 在p型扩散区域上形成电极，在n型扩散区域形成电极。 在p基板的后表面上形成电极。 P-衬底和n-层构成反向偏置状态的二极管。 结果，与传统的分压电阻电路相比，功耗降低。

公开(公告)号：US08674471B2

公开(公告)日：2014-03-18

申请号：US13596209

申请日：2012-08-28

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L21/70 ,  H01L21/762

CPC分类号： H02J7/022 ,  H01L27/0629 ,  H01L27/0635 ,  H03K17/6871 ,  H03K17/6872 ,  H03K17/6874 ,  H03K19/017509 ,  Y02B40/90

摘要： A semiconductor device supplying a charging current to a charging-target element includes: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type formed on a main surface of the semiconductor layer and having a first node coupled to a first electrode of the charging-target element and a second node coupled to a power supply potential node supplied with a power supply voltage; a second semiconductor region of the first conductivity type formed in a surface of the first semiconductor region at a distance from the semiconductor layer and having a third node coupled to the power supply potential node; and a charge carrier drift restriction portion restricting drift of charge carrier from the third node to the semiconductor layer.

摘要翻译： 向充电目标元件提供充电电流的半导体器件包括：第一导电类型的半导体层; 第二导电类型的第一半导体区域形成在半导体层的主表面上并且具有耦合到充电目标元件的第一电极的第一节点和耦合到被提供有电源的电源电位节点的第二节点 电压; 第一导电类型的第二半导体区域形成在距离半导体层一定距离的第一半导体区域的表面中，并且具有耦合到电源电位节点的第三节点; 以及电荷载流子漂移限制部分，其限制载流子从第三节点到半导体层的漂移。

公开(公告)号：US08093660B2

公开(公告)日：2012-01-10

申请号：US12205973

申请日：2008-09-08

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L27/06

CPC分类号： H01L27/0722 ,  H01L27/0248 ,  H01L29/78 ,  H03K17/0406 ,  H03K17/567

摘要： A voltage mitigating element mitigating a voltage applied across a gate insulating film in an off state of an insulated gate bipolar transistor (IGBT) is arranged to a gate electrode node of a P-channel MOS transistor provided for suppressing flow-in of holes at the time of turn-off of the IGBT. Withstanding voltage characteristics are improved and an occupation area thereof is reduced while maintaining switching characteristics and a low on-resistance of an insulated gate bipolar transistor.

摘要翻译： 在绝缘栅双极晶体管（IGBT）的截止状态下减轻施加在栅极绝缘膜上的电压的电压缓解元件被布置到P沟道MOS晶体管的栅电极节点，用于抑制在 IGBT关断时间。 提高了耐电压特性，并且在保持绝缘栅双极晶体管的开关特性和低导通电阻的同时降低占用面积。

公开(公告)号：US07755168B2

公开(公告)日：2010-07-13

申请号：US11738039

申请日：2007-04-20

申请人： Tomohide Terashima ,  Shiori Uota

发明人： Tomohide Terashima ,  Shiori Uota

IPC分类号： H01L29/70

CPC分类号： H01L29/735 ,  H01L29/0692 ,  H01L29/0821

摘要： A semiconductor device has a first conductivity-type first semiconductor region, a second conductivity-type second semiconductor region and a second conductivity-type third semiconductor region both located on or above the first semiconductor region, a second conductivity-type fourth semiconductor region between the second semiconductor region and the third semiconductor region, and a first conductivity-type fifth semiconductor region between the third semiconductor region and the fourth semiconductor region. The fourth semiconductor region and the fifth semiconductor region are electrically connected by a conductive member. A distance between the fourth semiconductor region and the third semiconductor region is larger than a width of the fourth semiconductor region.

摘要翻译： 半导体器件具有位于第一半导体区域上方或上方的第一导电型第一半导体区域，第二导电型第二半导体区域和第二导电型第三半导体区域，位于第一半导体区域之间的第二导电型第四半导体区域 第二半导体区域和第三半导体区域，以及在第三半导体区域和第四半导体区域之间的第一导电类型的第五半导体区域。 第四半导体区域和第五半导体区域通过导电构件电连接。 第四半导体区域和第三半导体区域之间的距离大于第四半导体区域的宽度。

公开(公告)号：US6153915A

公开(公告)日：2000-11-28

申请号：US70915

申请日：1998-05-04

申请人： Fumitoshi Yamamoto ,  Tomohide Terashima

发明人： Fumitoshi Yamamoto ,  Tomohide Terashima

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/10 ,  H01L29/41 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/1087 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0921

摘要： In a semiconductor device and a method of manufacturing the same according to the invention, a p-type diffusion region for electrically connecting a back gate region and an electrode layer together is formed at a source region. Thereby, both of source region and p-type diffusion region are electrically connected to the electrode layer, so that the source region and the back gate region are maintained at the same potential. As a result, it is possible to provide the semiconductor device and the method of manufacturing the same which can suppress operation of a parasitic bipolar transistor formed in the semiconductor device even if a gate electrode has a large width.

摘要翻译： 在根据本发明的半导体器件及其制造方法中，在源极区域形成用于将背栅极区域和电极层电连接的p型扩散区域。 由此，源极区域和p型扩散区域都与电极层电连接，使得源极区域和背面栅极区域保持相同的电位。 结果，即使栅电极具有大的宽度，也可以提供能够抑制形成在半导体器件中的寄生双极晶体管的工作的半导体器件及其制造方法。

公开(公告)号：US5894156A

公开(公告)日：1999-04-13

申请号：US739713

申请日：1996-10-29

申请人： Tomohide Terashima ,  Kazuhiro Shimizu

发明人： Tomohide Terashima ,  Kazuhiro Shimizu

IPC分类号： H01L29/78 ,  H01L27/06 ,  H01L27/08 ,  H01L29/06 ,  H01L29/08 ,  H01L27/092

CPC分类号： H01L29/7816 ,  H01L27/0629 ,  H01L29/063 ,  H01L29/0878 ,  Y10S257/90

摘要： A resurf structure is provided which includes an n type diffusion region surrounded by a n- diffusion region, in which a part of the joined combination of the n type diffusion region and the n- diffusion region is separated by a narrow p- substrate region in between. An aluminum lead is provided between the separated n- diffusion regions, and a signal is level shifted. A high voltage semiconductor device which includes a small area high voltage isolation region is obtained without process cost increase.

摘要翻译： 提供了一种再现结构，其包括由n型扩散区域包围的n型扩散区域，其中n型扩散区域和n型扩散区域的接合组合的一部分被窄的p-衬底区域分开 之间。 在分离的n-扩散区域之间设置铝引线，并且信号被电平移位。 获得包括小面积高电压隔离区域的高电压半导体器件，而不会增加工艺成本。