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124 条记录 (耗时 0.025 秒)

    Method for coupling logic blocks using low threshold pass transistors
    81.
    发明授权
    Method for coupling logic blocks using low threshold pass transistors 有权
    使用低阈值传递晶体管耦合逻辑块的方法

    公开(公告)号：US06489804B1

    公开(公告)日：2002-12-03

    申请号：US09872786

    申请日：2001-06-01

    申请人： James B. Burr

    发明人： James B. Burr

    IPC分类号： H03K19173

    CPC分类号： H03K19/17784 ,  H03K17/063 ,  H03K19/17728 ,  H03K19/17792

    摘要： Programmable logic structures include logic blocks that operate at very low supply voltages. According to the invention, a pass transistor is positioned between logic blocks. Since the logic blocks of the invention operate at very low supply voltages, the pass transistor can be overdriven on, thereby reducing the added resistance. In one embodiment of the invention, the pass transistor is a low threshold transistor. In this embodiment, the pass transistor is also overdriven off to reduce leakage current and further isolate the logic blocks.

    摘要翻译： 可编程逻辑结构包括在非常低的电源电压下工作的逻辑块。 根据本发明，传输晶体管位于逻辑块之间。 由于本发明的逻辑块在非常低的电源电压下工作，所以传输晶体管可能被过载驱动，从而降低了增加的电阻。 在本发明的一个实施例中，传输晶体管是低阈值晶体管。 在该实施例中，传输晶体管也被过驱动以减少泄漏电流并进一步隔离逻辑块。

    Method for engineering the threshold voltage of a device using buried wells
    82.
    发明授权
    Method for engineering the threshold voltage of a device using buried wells 有权
    使用埋井设备的阈值电压的方法

    公开(公告)号：US06489224B1

    公开(公告)日：2002-12-03

    申请号：US09872419

    申请日：2001-05-31

    申请人： James B. Burr

    发明人： James B. Burr

    IPC分类号： H01L21425

    CPC分类号： H01L21/823892

    摘要： Buried platform wells are specifically used to electrically interact with the platform transistors of the invention. The dopant concentration distribution of the buried platform wells is used to change the threshold voltage of the platform transistors of the invention by introducing a tail dopant concentration into the active region of the platform transistors. The platform transistors of the invention can also be used in conjunction with standard transistors, on a single structure, to provide both low and relatively high threshold voltage transistors on a single structure. Consequently, using the method and structure of the invention, considerable versatility and design flexibility are achieved with minimum additional structural complexity.

    摘要翻译： 埋地平台井专门用于与本发明的平台晶体管电相互作用。 掩埋平台阱的掺杂剂浓度分布用于通过将尾掺杂剂浓度引入平台晶体管的有源区来改变本发明的平台晶体管的阈值电压。 本发明的平台晶体管也可以与单个结构上的标准晶体管结合使用，以在单个结构上提供低和相对高的阈值电压晶体管。 因此，使用本发明的方法和结构，以最小的附加结构复杂性实现了相当多的通用性和设计灵活性。

    Low voltage latch with uniform stack height
    83.
    发明授权
    Low voltage latch with uniform stack height 有权
    具有均匀堆叠高度的低压闩锁

    公开(公告)号：US06472919B1

    公开(公告)日：2002-10-29

    申请号：US09872787

    申请日：2001-06-01

    申请人： James B. Burr

    发明人： James B. Burr

    IPC分类号： H03K3356

    CPC分类号： H03K3/356156 ,  H03K3/012

    摘要： Low voltage latches are designed such that all the transistors included in the latch are low threshold transistors and voltage scalability of the latches of the invention is further increased by designing latches with uniform stack height components. One embodiment of the invention allows for minimum supply voltages of 60 millivolts, an improvement of over thirteen hundred percent compared with the typical prior art minimum voltage requirement of 800 millivolts.

    摘要翻译： 低压锁存器被设计成使得包括在锁存器中的所有晶体管都是低阈值晶体管，并且通过设计具有均匀堆栈高度分量的锁存器来进一步增加本发明的锁存器的电压可伸缩性。 与典型的现有技术的800毫伏的最小电压要求相比，本发明的一个实施例允许60毫伏的最小电源电压，改进超过百分之十三点。

    Method for reducing PN junction leakage
    84.
    发明授权
    Method for reducing PN junction leakage 有权
    减少PN结泄漏的方法

    公开(公告)号：US06348372B1

    公开(公告)日：2002-02-19

    申请号：US09648867

    申请日：2000-08-25

    申请人： James B. Burr

    发明人： James B. Burr

    IPC分类号： H01L218238

    CPC分类号： H01L21/761 ,  H01L27/0921 ,  H01L27/1203

    摘要： To reduce p-n junction leakage at the boundary between lightly doped wells formed in lightly doped bulk materials, a high concentration region is implanted at the junction. The high concentration region contains a relatively high dopant level, and thus reduces the width of the depletion region at the junction. The reduced width of the depletion region in turn reduces junction leakage.

    摘要翻译： 为了减少在轻掺杂的体材料中形成的轻掺杂阱之间的边界处的p-n结泄漏，在该结处注入高浓度区域。 高浓度区域含有相当高的掺杂剂水平，因此降低了在结处的耗尽区域的宽度。 耗尽区域的减小的宽度又减少了结漏电。

    Low threshold voltage, high performance junction transistor
    85.
    发明授权
    Low threshold voltage, high performance junction transistor 失效
    低阈值电压，高性能结晶体管

    公开(公告)号：US5719422A

    公开(公告)日：1998-02-17

    申请号：US831659

    申请日：1997-04-09

    申请人： James B. Burr ,  Michael P. Brassington

    发明人： James B. Burr ,  Michael P. Brassington

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L27/088

    CPC分类号： H01L29/6659 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/7832 ,  H01L29/7833

    摘要： Low threshold voltage MOS devices having buried electrodes are disclosed herein. Such devices have source and drain regions which include tip regions and plug regions. The buried electrodes have bottom boundaries located above the bottoms of the plug regions. The buried electrode has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. The exact dopant concentrations and locations of the buried electrodes should be provided such that punch through is avoided in MOS devices.

    摘要翻译： 本文公开了具有埋电极的低阈值电压MOS器件。 这样的器件具有源极和漏极区域，其包括尖端区域和插塞区域。 掩埋电极具有位于插塞区域的底部之上的底部边界。 掩埋电极具有与器件的体积相同的导电类型（尽管在较高的掺杂剂浓度），当然，与器件的源极和漏极相反的导电类型。 应提供掩埋电极的确切掺杂剂浓度和位置，使MOS器件避免穿通。

    Software controlled transistor body bias
    88.
    发明授权
    Software controlled transistor body bias 有权
    软件控制晶体管体偏置

    公开(公告)号：US08370785B2

    公开(公告)日：2013-02-05

    申请号：US13168896

    申请日：2011-06-24

    申请人： David R. Ditzel ,  James B. Burr

    发明人： David R. Ditzel ,  James B. Burr

    IPC分类号： G06F17/50

    CPC分类号： G06F17/50 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    摘要： Software controlled transistor body bias. A target frequency is accessed. Using software, transistor body-biasing values are determined for the target frequency in order to enhance a characteristic of a circuit. The bodies of the transistors are biased based on the body-biasing values, wherein the characteristic is enhanced.

    摘要翻译： 软件控制晶体管体偏置。 访问目标频率。 使用软件，为了提高电路的特性，确定了目标频率的晶体管体偏置值。 晶体管的主体基于主体偏置值被偏置，其中特性被增强。