公开(公告)号：US20120012980A1

公开(公告)日：2012-01-19

申请号：US13165191

申请日：2011-06-21

申请人： DAVID VACLAV HORAK ,  Shom Ponoth ,  Hosadurga Shobha ,  Chih-Chao Yang

发明人： DAVID VACLAV HORAK ,  Shom Ponoth ,  Hosadurga Shobha ,  Chih-Chao Yang

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/88 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/3212

摘要： A semiconductor capacitor and its method of fabrication are disclosed. A non-linear nitride layer is used to increase the surface area of a capacitor plate, resulting in increased capacitance without increase in chip area used for the capacitor.

摘要翻译： 公开了一种半导体电容器及其制造方法。 使用非线性氮化物层来增加电容器板的表面积，导致增加的电容，而不增加用于电容器的芯片面积。

公开(公告)号：US20110285021A1

公开(公告)日：2011-11-24

申请号：US13191090

申请日：2011-07-26

申请人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Fenton R. McFeely

发明人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Fenton R. McFeely

IPC分类号： H01L23/52 ,  B82Y99/00

CPC分类号： H01L21/76826 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure that includes a dielectric material having a dielectric constant of about 3.0 or less is provided. This low k dielectric material has at least one conductive material having an upper surface embedded therein. The dielectric material also has a surface layer that is made hydrophobic prior to the formation of the noble metal cap. The noble metal cap is located directly on the upper surface of the at least one conductive material. Because of the presence of the hydrophobic surface layer on the dielectric material, the noble metal cap does not substantially extend onto the hydrophobic surface layer of the dielectric material that is adjacent to the at least one conductive material and no metal residues from the noble metal cap deposition form on this hydrophobic dielectric surface.

摘要翻译： 提供了包括具有约3.0或更小介电常数的介电材料的互连结构。 该低k电介质材料具有至少一个具有嵌入其中的上表面的导电材料。 电介质材料还具有在形成贵金属盖之前被制成疏水性的表面层。 贵金属盖直接位于至少一个导电材料的上表面上。 由于在电介质材料上存在疏水表面层，贵金属盖基本上不会延伸到与至少一种导电材料相邻的电介质材料的疏水表面层上，并且没有贵金属帽的金属残留物 沉积形式在该疏水电介质表面上。

公开(公告)号：US08023305B2

公开(公告)日：2011-09-20

申请号：US12136091

申请日：2008-06-10

申请人： Michael C. Gaidis ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  John K. DeBrosse ,  Louis L. C. Hsu ,  Carl Radens ,  Keith Kwong-Hon Wong ,  Chih-Chao Yang

发明人： Michael C. Gaidis ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  John K. DeBrosse ,  Louis L. C. Hsu ,  Carl Radens ,  Keith Kwong-Hon Wong ,  Chih-Chao Yang

IPC分类号： G11C19/02 ,  G11C19/08

CPC分类号： G11C19/0841 ,  B82Y10/00 ,  G11C5/02 ,  G11C11/161 ,  G11C11/1675 ,  Y10T29/53165

摘要： A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.

摘要翻译： 具有写入/读取功能的磁畴壁存储装置包括多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个不连续性，以便于 域墙位置; 与每个移位寄存器结构相关联的磁读取元件; 以及与所述移位寄存器结构中的每一个相关联的磁写元件，所述磁写入元件还包括单个写入线，所述单个写入线的纵轴基本上与所述共面移位寄存器结构中的每一个的纵向轴线正交。

公开(公告)号：US08003520B2

公开(公告)日：2011-08-23

申请号：US12972808

申请日：2010-12-20

申请人： Griselda Bonilla ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang

发明人： Griselda Bonilla ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L23/5222 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and containing cylindrical holes. The hard mask and the low-k material layer therebelow are etched to form cavities. A conductive material is plated on exposed metallic surfaces including portions of top surfaces of the metal feature to form metal pads. Metal silicide pads are formed by exposure of the metal pads to a silicon containing gas. An etch is performed to enlarge and merge the cavities in the low-k material layer. The metal feature is protected from the etch by the metal silicide pads. An interconnect structure having an air gap and free of defects to surfaces of the metal feature is formed.

公开(公告)号：US07960276B2

公开(公告)日：2011-06-14

申请号：US12128713

申请日：2008-05-29

申请人： Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang ,  Keith Kwong Hon Wong

发明人： Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang ,  Keith Kwong Hon Wong

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76873 ,  H01L2221/1089

摘要： A conductor-dielectric interconnect structure is fabricated by providing a structure comprising a dielectric layer having a patterned feature therein; depositing a plating seed layer on the dielectric layer in the patterned feature; depositing a sacrificial seed layer on the plating seed layer in the via; reducing the thickness of the sacrificial seed layer by reverse plating; and plating a conductive metal on the sacrificial seed layer in the patterned feature. Also provided is a dielectric layer having a via therein; a plating seed layer on the dielectric layer in the patterned feature; and a discontinuous sacrificial seed layer located in the patterned feature.

摘要翻译： 通过提供包括其中具有图案化特征的电介质层的结构来制造导体 - 电介质互连结构; 在所述图案化特征中的所述电介质层上沉积电镀种子层; 在通孔的电镀种子层上沉积牺牲种子层; 通过反向电镀减少牺牲种子层的厚度; 以及在所述图案化特征中的所述牺牲种子层上镀覆导电金属。 还提供了其中具有通孔的电介质层; 图案化特征中的电介质层上的电镀种子层; 以及位于图案化特征中的不连续牺牲种子层。

公开(公告)号：US07952146B2

公开(公告)日：2011-05-31

申请号：US12709928

申请日：2010-02-22

申请人： Chih-Chao Yang ,  Shom Ponoth

发明人： Chih-Chao Yang ,  Shom Ponoth

IPC分类号： H01L21/00

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the electromigration problem that is exhibited by prior art interconnect structures, are provided. In accordance with the present invention, a grain growth promotion layer, which promotes the formation of a conductive region within the interconnect structure that has a bamboo microstructure and an average grain size of larger than 0.05 microns is utilized. The inventive structure has improved performance and reliability.

摘要翻译： 提供了单镶嵌型或双镶嵌型的互连结构及其形成方法，其基本上减少了现有技术互连结构所呈现的电迁移问题。 根据本发明，利用促进在互连结构内形成具有竹微结构和平均粒径大于0.05微米的导电区域的晶粒生长促进层。 本发明的结构具有改进的性能和可靠性。

公开(公告)号：US07927995B2

公开(公告)日：2011-04-19

申请号：US12541502

申请日：2009-08-14

申请人： Chih-Chao Yang ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Nicholas C. Fuller ,  Louis C. Hsu

发明人： Chih-Chao Yang ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Nicholas C. Fuller ,  Louis C. Hsu

IPC分类号： H01L21/44

CPC分类号： H01L23/5252 ,  H01L21/76843 ,  H01L21/76844 ,  H01L2924/0002 ,  H01L2924/00

摘要： An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.

摘要翻译： 提供了一种抗熔丝结构，其包括掩埋的导电的，例如作为反熔丝材料的金属层以及形成这种抗熔丝结构的方法。 根据本发明，本发明的抗熔丝结构包括互连之间的漏电介质区域。 当两个相邻的互连被偏置时，这些原始互连之间的电阻开始减小，并且引起时间依赖介质击穿TDDB现象。 也可以通过增加局部温度来加速相邻互连之间的电阻的降低。

公开(公告)号：US20110069425A1

公开(公告)日：2011-03-24

申请号：US12565802

申请日：2009-09-24

申请人： Louis L. Hsu ,  Xu Ouyang ,  Chih-Chao Yang

发明人： Louis L. Hsu ,  Xu Ouyang ,  Chih-Chao Yang

IPC分类号： H01G4/38 ,  H01L21/02 ,  H03K17/687

CPC分类号： H01L28/40 ,  H01L22/14 ,  H01L22/22 ,  H01L22/34 ,  H01L23/5223 ,  H01L27/0688 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  Y10T307/865 ,  H01L2924/00

摘要： A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.

摘要翻译： 模块化电容器阵列包括多个电容器模块。 每个电容器模块包括电容器和被配置为电气断开电容器的开关装置。 开关装置包括：感测单元，被配置为检测电容器的泄漏电平，使得如果泄漏电流超过预定电平，则开关装置电连接电容器。 每个电容器模块可以包括单个电容器板，两个电容器板或多于两个的电容器板。 泄漏传感器和开关装置用于电气断开任何电容器阵列的电容器模块，从而保护电容器阵列免于漏电。

公开(公告)号：US07911025B2

公开(公告)日：2011-03-22

申请号：US12127080

申请日：2008-05-27

申请人： Louis C. Hsu ,  Rajiv V. Joshi ,  Jack Allan Mandelman ,  Chih-Chao Yang

发明人： Louis C. Hsu ,  Rajiv V. Joshi ,  Jack Allan Mandelman ,  Chih-Chao Yang

IPC分类号： H01L23/525

CPC分类号： H01L23/5256 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor structure. Methods of making and programming the fuse/anti-fuse structures are also provided.

摘要翻译： 提供了用于熔丝/反熔丝结构的技术，包括内部导体结构，从内部导体结构向外间隔开的绝缘层，设置在绝缘层外部的外部导体结构，以及限定空腔的空腔限定结构， 其中所述空腔限定结构的至少一部分由所述内部导体结构，所述绝缘层和所述外部导体结构中的至少一个形成。 还提供了制造和编程保险丝/反熔丝结构的方法。

公开(公告)号：US07902061B2

公开(公告)日：2011-03-08

申请号：US12199407

申请日：2008-08-27

申请人： Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis C. Hsu ,  Carl Radens ,  Theodorus E. Standaert ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis C. Hsu ,  Carl Radens ,  Theodorus E. Standaert ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76852 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of making an interconnect structure: which includes providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric material; and depositing an encasing cap over the extended portion of the interconnect structure.

摘要翻译： 一种制造互连结构的方法，其包括在介电材料中提供互连结构，使介电材料凹陷，使得互连结构的一部分在电介质材料的上表面上方延伸; 以及在所述互连结构的延伸部分上沉积封装盖。