公开(公告)号：US07281152B2

公开(公告)日：2007-10-09

申请号：US10808571

申请日：2004-03-25

申请人： Masaya Tarui ,  Shinichi Kanno

发明人： Masaya Tarui ,  Shinichi Kanno

IPC分类号： G06F5/06 ,  G06F1/00 ,  H04L5/00

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A processor includes a clock signal generator generating clock signals; an operational processing part performing data processing which is divided into a plurality of execution units, in accordance with the clock signals; a storage storing data used when each execution unit is executed by the operational processing part; a data amount detector detecting amounts of the data stored in the storage per each execution unit; a clock frequency determining part determining a new clock frequency of the clock signals by using the amounts of the data, the clock signals being supplied newly to the operational processing part.

摘要翻译： 处理器包括产生时钟信号的时钟信号发生器; 操作处理部分，根据所述时钟信号执行被分成多个执行单元的数据处理; 当由所述操作处理部执行每个执行单元时使用的存储数据的存储器; 数据量检测器，检测每个执行单元存储在存储器中的数据量; 时钟频率确定部分，通过使用所述数据量来确定时钟信号的新时钟频率，所述时钟信号被新提供给所述操作处理部分。

公开(公告)号：US20060017459A1

公开(公告)日：2006-01-26

申请号：US11081589

申请日：2005-03-17

申请人： Shinichi Kanno ,  Masaya Tarui ,  Taku Ohneda ,  Riku Ogawa

发明人： Shinichi Kanno ,  Masaya Tarui ,  Taku Ohneda ,  Riku Ogawa

IPC分类号： H03K19/177

CPC分类号： H03K19/17752

摘要： A programmable logic circuit apparatus includes a programmable logic circuit that dynamically switches and operates a plurality of circuit blocks. The circuit blocks include a branch circuit block that performs branch processing and a plurality of child circuit blocks that selectively perform a plurality of kinds of processing on data obtained by the branch circuit block. The apparatus also includes a storage unit that stores data obtained by the branch circuit block and an identifier of a child circuit block into which the data is input. The identifier is associated with the data. The apparatus also includes a controller that causes the programmable logic circuit to process data associated with the same identifier as an identifier of a child circuit block being in operation in the programmable logic circuit, among the data stored in the storage unit, in preference to data associated with identifiers of other child circuit blocks.

摘要翻译： 可编程逻辑电路装置包括动态地切换和操作多个电路块的可编程逻辑电路。 电路块包括执行分支处理的分支电路块和对由分支电路块获得的数据选择性地执行多种处理的多个子电路块。 该装置还包括存储单元，其存储由分支电路块获得的数据和输入数据的子电路块的标识符。 标识符与数据相关联。 该装置还包括一个控制器，该控制器使可编程逻辑电路处理与存储在存储单元中的数据相当的与可编程逻辑电路中正在操作的子电路块的标识符相同的标识符的数据，优先于数据 与其他子电路块的标识符相关联。

公开(公告)号：US06988004B2

公开(公告)日：2006-01-17

申请号：US09858036

申请日：2001-05-15

申请人： Shinichi Kanno ,  Yasufumi Sato

发明人： Shinichi Kanno ,  Yasufumi Sato

IPC分类号： A61N1/18

CPC分类号： A61N1/326

摘要： The present invention comprises a method for stimulating angiogenesis. The method comprises the steps of electrically stimulating muscle below the threshold for muscle contraction.

摘要翻译： 本发明包括刺激血管发生的方法。 该方法包括以下步骤：电刺激肌肉收缩阈值以下的肌肉。

公开(公告)号：US20050268125A1

公开(公告)日：2005-12-01

申请号：US11128187

申请日：2005-05-13

申请人： Taku Ohneda ,  Shinichi Kanno ,  Masaya Tarui ,  Yukimasa Miyamoto ,  Riku Ogawa

发明人： Taku Ohneda ,  Shinichi Kanno ,  Masaya Tarui ,  Yukimasa Miyamoto ,  Riku Ogawa

IPC分类号： G06F1/32 ,  G06F1/08 ,  G06F1/30 ,  H03K19/00 ,  H03K19/173

CPC分类号： G06F1/3203 ,  G06F1/08 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： Programmable logic circuits are changeable circuit components based on circuit data. A circuit data memory stores a plurality of circuit data and performance requirements. A feature data memory stores feature data of each programmable logic circuit. A control unit calculates a minimum voltage of the plurality of programmable logic circuits to execute the plurality of circuit data based on the performance requirements, and selectively assigns the plurality of circuit data to the plurality of programmable logic circuits so that the performance requirement of circuit data assigned to each programmable logic circuit is within the operation range of the programmable logic circuit at the minimum voltage. A supply unit supplies the minimum voltage to the plurality of programmable logic circuits.

摘要翻译： 可编程逻辑电路是基于电路数据的可变电路组件。 电路数据存储器存储多个电路数据和性能要求。 特征数据存储器存储每个可编程逻辑电路的特征数据。 控制单元基于性能要求，计算多个可编程逻辑电路的最小电压，以执行多个电路数据，并且选择性地将多个电路数据分配给多个可编程逻辑电路，使得电路数据的性能要求 分配给每个可编程逻辑电路的可编程逻辑电路在最小电压范围内。 供电单元向多个可编程逻辑电路提供最小电压。

公开(公告)号：US20050138445A1

公开(公告)日：2005-06-23

申请号：US10960707

申请日：2004-10-08

申请人： Taku Ooneda ,  Shinichi Kanno ,  Masaya Tarui ,  Yukimasa Miyamoto

发明人： Taku Ooneda ,  Shinichi Kanno ,  Masaya Tarui ,  Yukimasa Miyamoto

IPC分类号： H01L21/822 ,  G06F1/26 ,  G06F1/32 ,  H01L21/82 ,  H01L27/04 ,  H03K19/00 ,  H03K19/173

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/3296 ,  H03K19/0008 ,  H03K19/0016 ,  H03K19/1736 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/17784 ,  H03K19/17788 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/172

摘要： A logic circuit system with power consumption that is reduced by automatically varying the clock frequency and operating voltage according to processing capability imposed on programmable logic circuits. The programmable logic circuits are capable of achieving plural circuit functions dynamically and can change realized circuit functions during operation. In addition, the system has a voltage supply portion for supplying a voltage to the programmable logic circuits, a clock signal supply portion for supplying a clock signal to the programmable logic circuits, a change control portion for changing the circuit functions realized by the programmable logic circuits to any one of the circuit functions, an operation time measuring portion for measuring the operation times of the programmable logic circuits to perform processing to achieve the circuit functions, respectively, and a clock-and-voltage determination portion for determining the frequency of the clock signal and the voltage, using the operation times.

摘要翻译： 通过根据施加在可编程逻辑电路上的处理能力自动改变时钟频率和工作电压，降低功耗的逻辑电路系统。 可编程逻辑电路能够动态地实现多个电路功能，并且可以在操作期间改变实现的电路功能。 此外，系统具有用于向可编程逻辑电路提供电压的电压供应部分，用于向可编程逻辑电路提供时钟信号的时钟信号提供部分，用于改变可编程逻辑实现的电路功能的改变控制部分 电路中的任何一个电路功能，操作时间测量部分，用于分别测量可编程逻辑电路的操作时间以执行分别执行电路功能的处理;以及时钟和电压确定部分，用于确定 时钟信号和电压，使用操作时间。

公开(公告)号：US20050110518A1

公开(公告)日：2005-05-26

申请号：US10948702

申请日：2004-09-24

申请人： Shinichi Kanno ,  Yukimasa Miyamoto ,  Masaya Tarui ,  Taku Ooneda

发明人： Shinichi Kanno ,  Yukimasa Miyamoto ,  Masaya Tarui ,  Taku Ooneda

IPC分类号： G06F11/00 ,  G06F9/06 ,  G06F15/76 ,  G06F17/50 ,  H03K19/173 ,  H03K19/177

CPC分类号： G06F17/5054

摘要： A logic circuit apparatus that allocates process capability to unit circuits operated in a time divisional manner, including a circuit arrangement information memory which stores circuit arrangement information corresponding to each of plurality of unit circuits, and a programmable logic circuit with a circuit arrangement which can be reconfigured by employing the circuit arrangement information while the programmable logic circuit is being operated, a process data memory which stores both input data and output data related to a process operation of each of the circuits, and a controller which monitors a storage amount of the input data and/or a storage amount of the output data corresponding to each unit circuit, and which controls reconfiguration of the circuit arrangement of the programmable logic circuit when the storage amount satisfies a certain condition.

摘要翻译： 一种分时处理能力的逻辑电路装置，包括一个电路布置信息存储器，该电路布置信息存储器存储与多个单元电路中的每一个相对应的电路布置信息，以及一个可编程逻辑电路，该电路布置可以是 通过在可编程逻辑电路正在运行时采用电路布置信息来重新配置，存储输入数据和与每个电路的处理操作相关的输出数据的处理数据存储器，以及监视输入的存储量的控制器 数据和/或对应于每个单元电路的输出数据的存储量，并且当存储量满足一定条件时，控制可编程逻辑电路的电路装置的重新配置。

公开(公告)号：US06611870B1

公开(公告)日：2003-08-26

申请号：US09136513

申请日：1998-08-19

申请人： Shigehiro Asano ,  Tatsunori Kanai ,  Shinichi Kanno ,  Seiji Maeda

发明人： Shigehiro Asano ,  Tatsunori Kanai ,  Shinichi Kanno ,  Seiji Maeda

IPC分类号： G06F1516

CPC分类号： G06F13/385

摘要： A server device and a communication connection scheme capable of expanding the memory bandwidth and thereby expanding the power to transmit Web data to the network are disclosed. Network cards are detachably attached to a host machine (main machine). Each network card contains a processor, a memory, and a network interface unit, where data are transmitted to the network from a memory on the network card and the memory bandwidth expansion is realized by the presence of a plurality of network cards. In addition, using a memory of the network card as a cache, the load on the host machine is reduced by transmitting data from this memory to the network when the data exists on the memory and a certain condition is satisfied.

摘要翻译： 公开了能够扩展存储器带宽并由此扩展将网络数​​据传输到网络的功能的服务器设备和通信连接方案。 网卡可拆卸地连接到主机（主机）。 每个网卡包含处理器，存储器和网络接口单元，其中数据从网卡上的存储器发送到网络，并且通过存在多个网卡来实现存储器带宽扩展。 此外，使用网卡的存储器作为缓存，当数据存在于存储器上并且满足一定条件时，通过从该存储器向网络发送数据来减少主机上的负载。

公开(公告)号：US06295560B1

公开(公告)日：2001-09-25

申请号：US09205368

申请日：1998-12-04

申请人： Shinichi Kanno ,  Shigehiro Asano

发明人： Shinichi Kanno ,  Shigehiro Asano

IPC分类号： G06F1300

CPC分类号： G06F9/5083

摘要： A data delivery system capable of distributing processing loads on the data supply side without providing the control processor, in which clients can receive data delivery without becoming conscious of the switching of processors that carry out the data delivery, is disclosed. In this data delivery system, a request from the client to the data delivery system is always received by all the data delivery units according to the shared lower layer address, while a response to the connection request is made by only one data delivery unit which has the response right at that moment using the unique lower layer address of that data delivery unit. In this way, it appears to the client as if the request is always made with respect to the same correspondent, while at the data supply side, the data delivery unit for responding to the client is appropriately switched by appropriately transferring the response right so as to realize the load distribution within the data delivery system.

摘要翻译： 公开了一种能够在不提供控制处理器的情况下在数据提供侧分配处理负荷的数据传送系统，其中客户端可以在不意识到进行数据传送的处理器的切换的情况下接收数据传送。 在该数据传送系统中，由所有数据传送单元总是按照共享的下层地址接收来自客户端到数据传送系统的请求，而对连接请求的响应仅由一个数据传送单元进行， 此时使用该数据传送单元的唯一下层地址的响应权限。 以这种方式，对于客户端来说，似乎总是针对相同的记者进行请求，而在数据提供端，通过适当地转移响应权来适当地切换用于响应客户端的数据传送单元，以便 实现数据传送系统内的负载分配。

公开(公告)号：US20130246721A1

公开(公告)日：2013-09-19

申请号：US13608086

申请日：2012-09-10

申请人： Kazuhiro FUKUTOMI ,  Shinichi Kanno

发明人： Kazuhiro FUKUTOMI ,  Shinichi Kanno

IPC分类号： G06F3/06

CPC分类号： G06F3/0661 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0616 ,  G06F3/0638 ,  G06F3/0659 ,  G06F3/0679

摘要： According to an embodiment, a controller includes a write control unit configured to make a control that converts data requested to be written by an external device into pieces of cluster data with a size of a cluster of a storage medium, compresses each piece of cluster data, determines a corresponding physical address of a write destination in the storage medium according to a predetermined rule, and writes the compressed pieces of cluster data to the storage medium using the physical address of the write destination. The write control unit also makes a control that writes a correspondence between the physical address and a corresponding logical address to a storage unit. The controller also includes a read control unit configured to a control that reads a piece of cluster data from the storage medium using an acquired physical address, and decompresses the read piece of cluster data.

摘要翻译： 根据实施例，控制器包括：写入控制单元，被配置为进行将被外部设备请求写入的数据转换成具有存储介质的集群的大小的集群数据的控制，压缩每个集群数据 根据预定规则确定存储介质中的写目的地的对应物理地址，并使用写目的地的物理地址将压缩的簇数据写入存储介质。 写入控制单元还进行将物理地址和对应的逻辑地址之间的对应写入存储单元的控制。 控制器还包括一个读取控制单元，该读取控制单元被配置为使用所获取的物理地址从存储介质读取一个集群数据的控制，并解压缩所读取的集群数据。

公开(公告)号：US20130238838A1

公开(公告)日：2013-09-12

申请号：US13603989

申请日：2012-09-05

申请人： Kazuhiro FUKUTOMI ,  Shinichi Kanno ,  Shigehiro Asano

发明人： Kazuhiro FUKUTOMI ,  Shinichi Kanno ,  Shigehiro Asano

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0859 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0873 ,  G06F2212/604 ,  G06F2212/7202 ,  G06F2212/7203

摘要： According to an embodiment, a controller is connected to an external storage device and controls access to a semiconductor storage device including blocks each including memory cell groups each having memory cells. The block includes pages associated with each memory cell group. A writing process for each memory cell group includes writing stages. The controller includes a determining unit configured to determine data to be transferred to the page required in the writing process for a first memory cell group before the writing stage first starts when the writing stage is performed; a reading unit configured to read the determined data from the semiconductor storage device and to store the read data in the external storage device before the writing stage starts; and a writing unit configured to perform the writing process using the data stored in the external storage device when the writing stage is performed.

摘要翻译： 根据实施例，控制器连接到外部存储装置，并且控制对包括各自包含存储单元的存储单元组的块的半导体存储装置的访问。 该块包括与每个存储器单元组相关联的页面。 每个存储单元组的写入过程包括写入阶段。 控制器包括：确定单元，被配置为在执行写入阶段时，在写入阶段首先开始之前，确定要传送到第一存储单元组的写入处理所需的页面的数据; 读取单元，其被配置为从所述半导体存储装置读取所确定的数据，并且在所述写入阶段开始之前将读取的数据存储在所述外部存储装置中; 以及写入单元，被配置为当执行写入阶段时，使用存储在外部存储装置中的数据执行写入处理。