公开(公告)号：US20050157526A1

公开(公告)日：2005-07-21

申请号：US11019321

申请日：2004-12-23

申请人： Satoru Hanzawa ,  Takeshi Sakata ,  Kazuhiko Kajigaya

发明人： Satoru Hanzawa ,  Takeshi Sakata ,  Kazuhiko Kajigaya

IPC分类号： G11C11/401 ,  G11C11/56 ,  G11C15/04 ,  G11C15/00

CPC分类号： G11C15/04 ,  G11C15/043

摘要： The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.

摘要翻译： 有效存储范围指定的IP地址，以减少必要条目的数量，从而提高TCAM的存储容量。 本发明的代表性手段是：存储信息（条目）和输入信息（比较信息或搜索关键字）是公共块码，使得任何位必须是逻辑值“1”; 匹配线是分层结构的，并且存储器单元被布置在多个子匹配线和多条搜索线的交叉点处; 此外，子匹配线分别通过子匹配检测器连接到主匹配线，并且主匹配检测器被布置在主匹配线上。

公开(公告)号：US20050105326A1

公开(公告)日：2005-05-19

申请号：US11009449

申请日：2004-12-13

申请人： Satoru Hanzawa ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： G11C11/15 ,  G11C5/00 ,  G11C7/00 ,  G11C11/00 ,  G11C11/16 ,  G11C11/34 ,  H01L27/22 ,  H01L31/0328

CPC分类号： G11C29/787 ,  G11C7/14 ,  G11C11/1673 ,  G11C11/1693

摘要： A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.

摘要翻译： 虚拟单元包括：多个第一存储单元MC，用于存储多个字线WR0至WR7与多个第一数据线D 0至D 7之间的交点处的“1”或“0” 多个用于存储“1”或“0”的第一虚拟单元MCH，布置在字线WR0至WR7和第一虚拟数据线之间的交点处，以及多个第二虚拟单元MCL，用于存储“0” “，布置在字线WR0至WR7之间的交点处和第二伪数据线DD 1之间。

公开(公告)号：US06680867B2

公开(公告)日：2004-01-20

申请号：US10357222

申请日：2003-02-04

申请人： Satoru Hanzawa ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： G11C700

CPC分类号： G11C29/787 ,  G11C7/14 ,  G11C11/1673 ,  G11C11/1693

摘要： A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.

摘要翻译： 虚拟单元包括多个用于存储“1”或“0”的第一存储单元MC，其布置在多个字线WR0至WR7与多个第一数据线D0至D7之间的交点处，多个第一 用于存储“1”或“0”的虚拟单元MCH，布置在字线WR0至WR7和第一虚拟数据线之间的交点处，以及多个第二虚拟单元MCL，用于存储“0” 字线WR0〜WR7与第二伪数据线DD1的交点。

公开(公告)号：US06677633B2

公开(公告)日：2004-01-13

申请号：US10408221

申请日：2003-04-08

申请人： Takeshi Sakata ,  Satoru Hanzawa ,  Hideyuki Matsuoka

发明人： Takeshi Sakata ,  Satoru Hanzawa ,  Hideyuki Matsuoka

IPC分类号： H01L2978

CPC分类号： H01L27/108 ,  H01L27/10823

摘要： In manufacturing a semiconductor memory by using conventional gain cells, it is difficult to integrate them similarly to 1T1C cells of a DRAM if mask alignment accuracy is considered. In order to achieve integration similarly to that of 1T1C cells by using gain cells, a memory cell block constituted as follows is used. A memory block (MCT) comprises a plurality of memory cells (MC0-MC3). Each memory cell includes a PMOS transistor (M0) for writing and an NMOS transistor (M1) for reading, and information is stored by holding electric charge in a storage node. The write transistors (M0) are arranged in parallel in a plurality of cells, each source-drain path is connected to a data line (DL). The read transistors (M1) are connected in series in a plurality of cells, and are connected to the data line (DL) via a block selection transistor (MB).

摘要翻译： 在通过使用常规增益单元制造半导体存储器时，如果考虑到掩模对准精度，则难以将其类似于DRAM的1T1C单元进行集成。 为了通过使用增益单元来实现与1T1C单元的集成相似的集成，使用如下构成的存储单元块。 存储块（MCT）包括多个存储单元（MC0-MC3）。 每个存储单元包括用于写入的PMOS晶体管（M0）和用于读取的NMOS晶体管（M1），并且通过在存储节点中保持电荷来存储信息。 写入晶体管（M0）在多个单元中并联布置，每个源极 - 漏极路径连接到数据线（DL）。 读取晶体管（M1）串联连接在多个单元中，并通过块选择晶体管（MB）连接到数据线（DL）。

公开(公告)号：US06570206B1

公开(公告)日：2003-05-27

申请号：US10239417

申请日：2002-09-24

申请人： Takeshi Sakata ,  Satoru Hanzawa ,  Hideyuki Matsuoka

发明人： Takeshi Sakata ,  Satoru Hanzawa ,  Hideyuki Matsuoka

IPC分类号： H01L2978

CPC分类号： G11C11/405 ,  G11C11/4097 ,  H01L27/108 ,  H01L27/10873

摘要： In manufacturing a semiconductor memory by using conventional gain cells, it is difficult to integrate them similarly to 1T1C cells of a DRAM if mask alignment accuracy is considered. In order to achieve integration similarly to that of 1T1C cells by using gain cells, a memory cell block constituted as follows is used. A memory block (MCT) comprises a plurality of memory cells (MC0-MC3). Each memory cell includes a PMOS transistor (M0) for writing and an NMOS transistor (M1) for reading, and information is stored by holding electric charge in a storage node. The write transistors (M0) are arranged in parallel in a plurality of cells, each source-drain path is connected to a data line (DL). The read transistors (M1) are connected in series in a plurality of cells, and are connected to the data line (DL) via a block selection transistor (MB).

摘要翻译： 在通过使用常规增益单元制造半导体存储器时，如果考虑到掩模对准精度，则难以将其类似于DRAM的1T1C单元进行集成。 为了通过使用增益单元来实现与1T1C单元的集成相似的集成，使用如下构成的存储单元块。 存储块（MCT）包括多个存储单元（MC0-MC3）。 每个存储单元包括用于写入的PMOS晶体管（M0）和用于读取的NMOS晶体管（M1），并且通过在存储节点中保持电荷来存储信息。 写入晶体管（M0）在多个单元中并联布置，每个源极 - 漏极路径连接到数据线（DL）。 读取晶体管（M1）串联连接在多个单元中，并通过块选择晶体管（MB）连接到数据线（DL）。

公开(公告)号：US06452858B1

公开(公告)日：2002-09-17

申请号：US09706374

申请日：2000-11-03

申请人： Satoru Hanzawa ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： G11C11407

CPC分类号： G11C8/08 ,  G11C11/4074 ,  G11C11/4085

摘要： A semiconductor device to output voltages at three levels to a word driver while alleviating the breakdown voltage in the MOS transistor. This invention is comprised of a breakdown-voltage reducing MOS transistor inserted in the word driver and two NMOS transistors to supply a read-out voltage to a word line. The word driver is moreover controlled by different voltage amplitudes on the main word lines and the common word lines.

摘要翻译： 一种半导体器件，用于将三电平的电压输出到字驱动器，同时减轻MOS晶体管中的击穿电压。 本发明包括插入字驱动器中的击穿电压降低MOS晶体管和两个NMOS晶体管，以将读出电压提供给字线。 此外，字驱动器通过主字线和公用字线上的不同电压幅度进行控制。

公开(公告)号：US08773919B2

公开(公告)日：2014-07-08

申请号：US13300139

申请日：2011-11-18

申请人： Seiji Miura ,  Satoru Hanzawa

发明人： Seiji Miura ,  Satoru Hanzawa

IPC分类号： G11C7/00 ,  G11C13/00 ,  G11C8/08 ,  G11C8/18

CPC分类号： G11C13/0007 ,  G11C8/08 ,  G11C8/18 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0088 ,  G11C2211/5623

摘要： In a phase change memory, when M bit (8 bits=1 byte) data is written, erase operation and program operation are performed in units of n bit (M>n) data. Further, when M bit data is written, program operation is performed in units of the n bit (M>n) data. Further, when M bit data is read from the memory cell, read operation is performed in units of the n bit (M>n) data. For example, when the data is written into to the phase change memory, the data is not overwritten but program is performed after once erasing the target memory cell. The data size for erasure and the data size for program are made equal. Erase and program operation are performed only for the demanded data size.

摘要翻译： 在相变存储器中，当写入M位（8位= 1字节）数据时，以n位（M> n）数据为单位执行擦除操作和编程操作。 此外，当写入M位数据时，以n位（M> n）数据为单位执行编程操作。 此外，当从存储单元读取M位数据时，以n位（M> n）数据为单位执行读操作。 例如，当数据被写入相变存储器时，数据不被重写，而是在擦除目标存储单元之后执行程序。 擦除的数据大小和程序的数据大小相等。 擦除和编程操作仅针对所需的数据大小执行。

公开(公告)号：US08711637B2

公开(公告)日：2014-04-29

申请号：US13300139

申请日：2011-11-18

申请人： Seiji Miura ,  Satoru Hanzawa

发明人： Seiji Miura ,  Satoru Hanzawa

IPC分类号： G11C7/00

摘要： In a phase change memory, when M bit (8 bits=1 byte) data is written, erase operation and program operation are performed in units of n bit (M>n) data. Further, when M bit data is written, program operation is performed in units of the n bit (M>n) data. Further, when M bit data is read from the memory cell, read operation is performed in units of the n bit (M>n) data. For example, when the data is written into to the phase change memory, the data is not overwritten but program is performed after once erasing the target memory cell. The data size for erasure and the data size for program are made equal. Erase and program operation are performed only for the demanded data size.

公开(公告)号：US08634257B2

公开(公告)日：2014-01-21

申请号：US13466866

申请日：2012-05-08

申请人： Satoru Hanzawa ,  Hiroyuki Minemura

发明人： Satoru Hanzawa ,  Hiroyuki Minemura

IPC分类号： G11C7/22

CPC分类号： H01L27/2454 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2213/18 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/124 ,  H01L45/144

摘要： A semiconductor storage device crystallizes variable resistive element material layers arranged on side surfaces of multiple semiconductor layers in a stacked structure concurrently by applying a first current to any one of semiconductor layers in the stacked structure, and thereafter applies a second current to semiconductor layers other than a semiconductor layer to which the first current was applied.

摘要翻译： 半导体存储装置通过向堆叠结构中的任一个半导体层施加第一电流，同时以层叠结构使配置在多个半导体层的侧面上的可变电阻元件材料层结晶化，然后向第二电流施加除了 施加了第一电流的半导体层。

公开(公告)号：US08319204B2

公开(公告)日：2012-11-27

申请号：US12373185

申请日：2006-07-21

申请人： Motoyasu Terao ,  Satoru Hanzawa ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki

发明人： Motoyasu Terao ,  Satoru Hanzawa ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki

IPC分类号： H01L45/00 ,  H01L27/04

CPC分类号： G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

摘要： A recording layer 52 made of a chalcogenide material which stores a high-resistance state of a high electrical resistance value and a low-resistance state of a low electrical resistance value is used as a memory element RM in a memory cell region, and it is formed so that a concentration of Ga or In of a first layer 52a positioned on a lower electrode TP side of the recording layer 52 is higher than the corresponding concentration of a second layer 52b positioned on an upper electrode 53 side. For example, the recording layer is formed so that a content of Ga or In of the second layer is 5 atomic % or more smaller than that of the first layer. Also, a circuit which can reverse the voltage polarity between the upper electrode and the lower electrode in a set operation and a reset operation is provided.

摘要翻译： 作为存储单元区域中的存储元件RM，使用由存储高电阻值的高电阻状态和低电阻值的低电阻状态的硫族化物材料制成的记录层52， 使得位于记录层52的下电极TP侧的第一层52a中的Ga或In的浓度高于位于上电极53侧的第二层52b的相应浓度。 例如，记录层形成为使得第二层中的Ga或In的含量比第一层的含量低5原子％以上。 此外，提供了在设定操作和复位操作中可以反转上电极和下电极之间的电压极性的电路。