利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

318 条记录 (耗时 0.048 秒)

    Detecting the boundaries of memory in a RISC microprocessor architecture
    82.
    发明申请
    Detecting the boundaries of memory in a RISC microprocessor architecture 审中-公开

    公开(公告)号：US20070271442A1

    公开(公告)日：2007-11-22

    申请号：US11881284

    申请日：2007-07-26

    申请人： George Shaw ,  Martin McClurg ,  Bradley Jensen ,  Russell Fish ,  Charles Moore

    发明人： George Shaw ,  Martin McClurg ,  Bradley Jensen ,  Russell Fish ,  Charles Moore

    IPC分类号： G06F9/30

    CPC分类号： G06F12/0875 ,  G06F9/30014 ,  G06F9/3005 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/322 ,  G06F9/3824 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/3879 ,  G09G5/363 ,  G09G5/393 ,  G09G2360/121 ,  G09G2360/126

    摘要： A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status. The CPU contains both a high-performance, zero-operand, dual-stack architecture MPU, and an input-output processor (IOP) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand stack architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU and IOP to issue and complete instructions in a single clock cycle—each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.

    DISPLAY MEMORY, DRIVER CIRCUIT, DISPLAY, AND PORTABLE INFORMATION DEVICE
    83.
    发明申请
    DISPLAY MEMORY, DRIVER CIRCUIT, DISPLAY, AND PORTABLE INFORMATION DEVICE 审中-公开
    显示存储器，驱动电路，显示器和便携式信息设备

    公开(公告)号：US20070024606A1

    公开(公告)日：2007-02-01

    申请号：US11470823

    申请日：2006-09-07

    申请人： Katsutoshi Moriyama ,  Tomoya Ayabe ,  Taishi Mizuta

    发明人： Katsutoshi Moriyama ,  Tomoya Ayabe ,  Taishi Mizuta

    IPC分类号： G09G5/00

    CPC分类号： G09G3/3685 ,  G09G3/20 ,  G09G3/2003 ,  G09G3/3611 ,  G09G5/001 ,  G09G5/393 ,  G09G5/395 ,  G09G2310/027 ,  G09G2310/0297 ,  G09G2330/021 ,  G09G2330/026 ,  G09G2330/027 ,  G09G2360/126

    摘要： A display memory able to reduce power consumption, able to generate graphics at a high speed, and not needing memory mapping, a driver circuit, a display using the driver circuit, and a portable information apparatus, wherein a CPU read circuit is connected to one bit line of a display memory 7, a display read circuit is connected to the other bit line, a write circuit is connected to both bit lines, the CPU read circuit and write circuit are assigned to the access from the CPU, the display read circuit is assigned to the display screen display, and further the access from the CPU and the reading to the display screen are assigned to different two level periods of a clock signal of the memory and independently controlled. Further, a drive power supply of the display memory is divided and a drive power supply voltage is supplied to the display memory for every memory cell or for every plurality of memory cells.

    摘要翻译： 一种显示存储器，其能够降低功耗，能够以高速生成图形，并且不需要存储器映射，驱动电路，使用驱动电路的显示器和便携式信息装置，其中CPU读取电路连接到一个 显示存储器7的位线，显示读取电路连接到另一个位线，写入电路连接到两个位线，CPU读取电路和写入电路被分配给来自CPU的访问，显示读取电路 被分配给显示屏幕显示，并且进一步将来自CPU的访问和对显示屏幕的读取分配给存储器的时钟信号的不同的两个电平周期并且被独立控制。 此外，显示存储器的驱动电源被分割，并且驱动电源电压被提供给每个存储单元或每个存储单元的显示存储器。

    Liquid crystal display and driving method thereof
    87.
    发明申请
    Liquid crystal display and driving method thereof 审中-公开
    液晶显示及其驱动方法

    公开(公告)号：US20060145981A1

    公开(公告)日：2006-07-06

    申请号：US10535406

    申请日：2003-11-20

    申请人： Seung-Woo Lee ,  Young-Ki Kim ,  Jung-Hee Lee

    发明人： Seung-Woo Lee ,  Young-Ki Kim ,  Jung-Hee Lee

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3607 ,  G02F2001/134345 ,  G09G5/02 ,  G09G2300/0876 ,  G09G2360/126

    摘要： A device of driving a liquid crystal display including a plurality of pixels connected to gate lines and data lines and arranged in a matrix is provided. The driving device includes: a gray voltage generator (800) generating a plurality of gray voltages; an image signal modifier (600) receiving first image signals for a pixel row and second image signals for a next pixel row, selecting modified image signal depending on the first image signals and the second image signals, and outputting the modified image signals; and a data driver (500) selecting data voltages from the gray voltages based on the modified image signals from the image signal modifier and applying the data voltages to the pixels.

    摘要翻译： 提供一种驱动液晶显示器的装置，其包括连接到栅极线和数据线并以矩阵布置的多个像素。 驱动装置包括：产生多个灰度电压的灰度电压发生器（800） 接收用于像素行的第一图像信号和下一个像素行的第二图像信号的图像信号修改器（600），根据第一图像信号和第二图像信号选择修正图像信号，并输出修改的图像信号; 以及数据驱动器（500），基于来自图像信号修改器的修正图像信号，从灰度电压中选择数据电压，并将数据电压施加到像素。