公开(公告)号：US20060261397A1

公开(公告)日：2006-11-23

申请号：US11493074

申请日：2006-07-26

申请人： Kie Ahn ,  Leonard Forbes

发明人： Kie Ahn ,  Leonard Forbes

IPC分类号： H01L29/94

CPC分类号： H01L21/02181 ,  C23C14/08 ,  C23C16/405 ,  C23C16/45525 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02205 ,  H01L21/02269 ,  H01L21/0228 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/3141 ,  H01L21/3142 ,  H01L21/31604 ,  H01L21/31645 ,  H01L27/1085 ,  H01L27/10873 ,  H01L28/56 ,  H01L29/40114 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78 ,  H01L29/78657

摘要： Dielectric layers are provided configured with a layer of lanthanide oxide and a layer of hafnium oxide, where the layer of hafnium oxide is structured as one of more monolayers of hafnium oxide. In an embodiment, a dielectric layer may be arranged as a nanolaminate of hafnium oxide and a lanthanide oxide, with the layer of hafnium oxide structured as one of more monolayers of hafnium oxide.

摘要翻译： 提供介电层，其配置有镧系元素氧化物层和氧化铪层，其中氧化铪层被构造为更多的氧化铪单层之一。 在一个实施方案中，电介质层可以被布置为氧化铪和镧系元素氧化物的纳米级氨基酸盐，氧化铪层被构造为氧化铪的单层之一。

公开(公告)号：US07129128B2

公开(公告)日：2006-10-31

申请号：US09941827

申请日：2001-08-29

申请人： Ronald A. Weimer

发明人： Ronald A. Weimer

IPC分类号： H01L21/8242

CPC分类号： H01L21/02332 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02183 ,  H01L21/02337 ,  H01L21/3144 ,  H01L21/31604 ,  H01L27/0805 ,  H01L28/56 ,  H01L28/84

摘要： Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are provided. A self-limiting nitric oxide (NO) anneal of a polysilicon layer such as an HSG polysilicon capacitor electrode, at less than 800° C., is utilized to grow a thin oxide (oxynitride) layer of about 40 angstroms or less over the polysilicon layer. The NO anneal provides a nitrogen layer at the polysilicon-oxide interface that limits further oxidation of the polysilicon layer and growth of the oxide layer. The oxide layer is exposed to a nitrogen-containing gas to nitridize the surface of the oxide layer and reduce the effective dielectric constant of the oxide layer. The process is particularly useful in forming high K dielectric insulating layers such as tantalum pentoxide over polysilicon. The nitridized oxynitride layer inhibits oxidation of the underlying polysilicon layer in a post-treatment oxidizing anneal of the high K dielectric, thus maintaining the oxide layer as a thin layer over the polysilicon layer.

公开(公告)号：US07112539B2

公开(公告)日：2006-09-26

申请号：US10999608

申请日：2004-11-29

申请人： Jongho Lee ,  Nae-In Lee

发明人： Jongho Lee ,  Nae-In Lee

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7881 ,  H01L29/94

摘要： A multi-layer dielectric layer structure for a semiconductor device. The multi-layer dielectric layer structure comprises a silicate interface layer having a dielectric constant greater than that of silicon nitride and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises one or more ordered pairs of first and second layers. With the present invention, the dielectric constant of the high-k dielectric layer can be optimized while improving interface characteristics. With a higher crystallization temperature realized by forming the multi-layer structure, each of whose layers is not more than the critical thickness, leakage current can be reduced, thereby improving device performance.

公开(公告)号：US07105401B2

公开(公告)日：2006-09-12

申请号：US10930953

申请日：2004-09-01

申请人： Jung-hyun Lee ,  Yo-sep Min ,  Young-jin Cho

发明人： Jung-hyun Lee ,  Yo-sep Min ,  Young-jin Cho

IPC分类号： H01L21/8242

CPC分类号： H01L28/56 ,  H01L21/3141 ,  H01L21/321 ,  H01L27/0629 ,  H01L28/55 ,  H01L28/65

摘要： A capacitor for use in a semiconductor device, a method of fabricating the capacitor, and an electronic device adopting the capacitor, wherein the capacitor includes upper and lower electrodes, each formed of a platinum group metal; a thin dielectric layer disposed between the upper and lower electrodes; and a buffer layer disposed between the lower electrode and the thin dielectric layer, the buffer layer including a metal oxide of Group 3, 4, or 13. In an embodiment, the method of fabricating includes absorbing CO on a surface of a lower electrode of a platinum group metal, placing the lower electrode under a reducing atmosphere to produce a lattice oxygen, using the lattice oxygen to form a thin dielectric layer by performing an ALD process using a precursor for the thin dielectric layer, and forming an upper electrode of a platinum group metal on the thin dielectric layer.

摘要翻译： 一种用于半导体器件的电容器，制造该电容器的方法以及采用该电容器的电子器件，其中该电容器包括由铂族金属形成的上下电极; 设置在上电极和下电极之间的薄介电层; 以及设置在下电极和薄电介质层之间的缓冲层，缓冲层包括第3,4或13族的金属氧化物。在一个实施方案中，制造方法包括在下电极的表面上吸收CO 铂族金属，将下电极置于还原气氛下以产生晶格氧，使用晶格氧通过使用用于薄介电层的前体进行ALD工艺形成薄介电层，并形成上电极 铂族金属在薄介电层上。

公开(公告)号：US07101775B2

公开(公告)日：2006-09-05

申请号：US10911516

申请日：2004-08-05

申请人： Kazuhiro Eguchi ,  Seiji Inumiya ,  Yoshitaka Tsunashima

发明人： Kazuhiro Eguchi ,  Seiji Inumiya ,  Yoshitaka Tsunashima

IPC分类号： H01L21/3205

CPC分类号： H01L29/511 ,  C23C16/30 ,  C23C16/45523 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/28229 ,  H01L21/31604 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof, and a third region between the first and second regions, the metallic element contained in the silicon oxide film having a density distribution in a thickness direction of the silicon oxide film, a peak of the density distribution existing in the third region, and an electrode formed on the gate dielectrics.

公开(公告)号：US20060145233A1

公开(公告)日：2006-07-06

申请号：US11320385

申请日：2005-12-28

申请人： Kyong-Min Kim ,  Dong-Jun Kim ,  Kwang-Woon Lee

发明人： Kyong-Min Kim ,  Dong-Jun Kim ,  Kwang-Woon Lee

IPC分类号： H01L29/00 ,  H01L21/36

CPC分类号： H01L28/56 ,  H01L27/10852 ,  H01L28/57

摘要： A method of forming a capacitor of a semiconductor device is provided. In the method, a capacitor lower electrode is deposited on a semiconductor substrate and then a dielectric layer is deposited on the lower electrode. A dielectric barrier layer is deposited on an upper part of the dielectric layer. The dielectric barrier layer comprises a material for preventing degradation of a leakage current characteristic of the dielectric layer. The method further comprises depositing a capacitor upper electrode on an upper part of the dielectric barrier layer.

摘要翻译： 提供一种形成半导体器件的电容器的方法。 在该方法中，在半导体衬底上沉积电容器下电极，然后在下部电极上沉​​积电介质层。 介电阻挡层沉积在电介质层的上部。 电介质阻挡层包括用于防止介电层的漏电流特性劣化的材料。 该方法还包括在电介质阻挡层的上部上沉积电容器上电极。

公开(公告)号：US20060141698A1

公开(公告)日：2006-06-29

申请号：US11358524

申请日：2006-02-21

申请人： Ronald Weimer

发明人： Ronald Weimer

IPC分类号： H01L21/20 ,  H01L21/8242

CPC分类号： H01L21/02332 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02183 ,  H01L21/02337 ,  H01L21/3144 ,  H01L21/31604 ,  H01L27/0805 ,  H01L28/56 ,  H01L28/84

摘要： Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are provided. A self-limiting nitric oxide (NO) anneal of a polysilicon layer such as an HSG polysilicon capacitor electrode, at less than 800° C., is utilized to grow a thin oxide (oxynitride) layer of about 40 angstroms or less over the polysilicon layer. The NO anneal provides a nitrogen layer at the polysilicon-oxide interface that limits further oxidation of the polysilicon layer and growth of the oxide layer. The oxide layer is exposed to a nitrogen-containing gas to nitridize the surface of the oxide layer and reduce the effective dielectric constant of the oxide layer. The process is particularly useful in forming high K dielectric insulating layers such as tantalum pentoxide over polysilicon. The nitridized oxynitride layer inhibits oxidation of the underlying polysilicon layer in a post-treatment oxidizing anneal of the high K dielectric, thus maintaining the oxide layer as a thin layer over the polysilicon layer.

公开(公告)号：US07057874B2

公开(公告)日：2006-06-06

申请号：US11015082

申请日：2004-12-16

申请人： Takashi Nakamura

发明人： Takashi Nakamura

IPC分类号： H01G4/005

CPC分类号： H01L21/32051 ,  H01L21/76841 ,  H01L27/0805 ,  H01L28/55 ,  H01L28/56 ,  H01L28/60 ,  H01L28/65 ,  H01L28/75

摘要： A ferroelectric capacitor including a lower electrode, a ferroelectric layer and an upper electrode. A part of at least any one of the lower and upper electrodes is formed of a material selected from the group consisting of TiOx, TaOx, ReOx, WOx, IrO2, PtO2, RuOx, PdOx, and OsOx.

摘要翻译： 包括下电极，铁电层和上电极的铁电电容器。 下电极和上电极中的至少任何一个的一部分由选自TiO x，TaO x，ReO x，WO x，IrO 2，PtO 2 ，RuOx，PdOx和OsOx。

公开(公告)号：US07037730B2

公开(公告)日：2006-05-02

申请号：US09904112

申请日：2001-07-11

申请人： Cem Basceri ,  Gurtej S. Sandhu ,  Mark Visokay

发明人： Cem Basceri ,  Gurtej S. Sandhu ,  Mark Visokay

IPC分类号： H01L21/8242

CPC分类号： H01L28/56 ,  H01L27/10811

摘要： Stabilized capacitors and DRAM cells using high dielectric constant oxide dielectric materials such as Ta2O5 and BaxSr(1−x)TiO3, and methods of making such capacitors and DRAM cells are provided. A preferred method includes providing a conductive oxide electrode, depositing a first layer of a high dielectric constant oxide dielectric material on the conductive oxide electrode, oxidizing the conductive oxide electrode and the first layer of the high dielectric constant oxide dielectric material under oxidizing conditions, depositing a second layer of the high dielectric constant oxide dielectric material on the first layer of the dielectric, and depositing an upper layer electrode on the second layer of the high dielectric constant oxide dielectric material.

摘要翻译： 使用高介电常数氧化物介电材料如Ta 2 O 5和Ba x Sr（1-x）的稳定电容器和DRAM单元 ）和提供制造这种电容器和DRAM单元的方法。 优选的方法包括提供导电氧化物电极，在导电氧化物电极上沉积高介电常数氧化物介电材料的第一层，在氧化条件下氧化导电氧化物电极和高介电常数氧化物介电材料的第一层，沉积 在所述电介质的第一层上的所述高介电常数氧化物电介质材料的第二层，以及在所述高介电常数氧化物介电材料的第二层上沉积上层电极。

公开(公告)号：US07026674B2

公开(公告)日：2006-04-11

申请号：US10740439

申请日：2003-12-22

申请人： Takashi Nakagawa

发明人： Takashi Nakagawa

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L28/56 ,  H01L21/31691

摘要： A semiconductor memory device includes a capacitor which comprises a ferroelectric layer with the perovskite crystal structure which, being expressed by the general formula ABO3, contains lead (Pb) as the element A occupying lattice A and zirconium (Zr) and titanium (Ti) as the element B occupying lattice B, and a lower electrode and an upper electrode which are disposed to sandwich the ferroelectric layer. The ferroelectric layer has, both on the side of the lower electrode and on the side of the upper electrode, a region each, in which a ratio of Zr to Ti (a Zr/Ti ratio) is equal to or greater than a Zr/Ti ratio of the central section of the ferroelectric layer in the direction of thickness, and the Zr/Ti ratio of at least one of the regions on the side of the lower electrode and on the side of the upper electrode is greater than the Zr/Ti ratio of the central section.

摘要翻译： 一种半导体存储器件包括电容器，其包含由通式ABO 3表示的具有钙钛矿晶体结构的铁电体层，其含有作为构成晶格A的元素A的铅（Pb）和锆（ Zr）和作为元素B的钛（Ti）占据晶格B，以及下电极和上电极，以夹持铁电层。 铁电层在下电极侧和上电极侧均具有Zr与Ti的比（Zr / Ti比）等于或大于Zr / Ti的区域， 铁电层的中心部分的厚度方向的Ti比和下部电极的一侧的区域和上部电极的一侧的Zr / Ti比大于Zr / Ti中心部分的比例。