公开(公告)号：US20080214017A1

公开(公告)日：2008-09-04

申请号：US11967517

申请日：2007-12-31

申请人： Shigemi Murakawa ,  Toshikazu Kumai ,  Toshio Nakanishi

发明人： Shigemi Murakawa ,  Toshikazu Kumai ,  Toshio Nakanishi

IPC分类号： H01L21/31

CPC分类号： H01L21/28185 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02183 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02332 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/3143 ,  H01L21/31604 ,  H01L21/31612 ,  H01L21/31662 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  Y10S438/954 ,  Y10S438/981

摘要： A gate insulation film (104) of a MISFET (100) is constituted of a silicon oxide film (106), silicon nitride film (107), and high-permittivity film (108). The silicon oxide film (106) and silicon nitride film (107) are formed by microwave plasma processing with a radial line slot antenna.

摘要翻译： MISFET（100）的栅极绝缘膜（104）由氧化硅膜（106），氮化硅膜（107）和高介电常数膜（108）构成。 氧化硅膜（106）和氮化硅膜（107）通过具有径向线槽天线的微波等离子体处理形成。

公开(公告)号：US07420264B2

公开(公告)日：2008-09-02

申请号：US11400301

申请日：2006-04-07

申请人： Michael Goldstein

发明人： Michael Goldstein

IPC分类号： H01L23/58

CPC分类号： B81C1/00666 ,  B81B2201/042 ,  B81C2201/0167 ,  G02B5/0833 ,  G02B26/0833 ,  Y10S438/954

摘要： An optical device having a high reflector tunable stress coating includes a micro-electromechanical system (MEMS) platform, a mirror disposed on the MEMS platform, and a multiple layer coating disposed on the mirror. The multiple layer coating includes a layer of silver (Ag), a layer of silicon dioxide (SiO2) deposited on the layer of Ag, a layer of intrinsic silicon (Si) deposited on the layer of SiO2, and a layer of silicon oxynitride (SiOxNy) deposited on the layer of Si. The concentration of nitrogen is increased and/or decreased to tune the stress (e.g., tensile, none, compressive).

公开(公告)号：US07420243B2

公开(公告)日：2008-09-02

申请号：US11248691

申请日：2005-10-12

申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim

发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim

IPC分类号： H01L29/788

CPC分类号： H01L29/42352 ,  H01L21/28282 ,  H01L29/7923 ,  Y10S438/954

摘要： In a non-volatile memory device with a buried control gate, the effective channel length of the control gate is increased to restrain punchthrough, and a region for storing charge is increased for attaining favorably large capacity. A method of fabricating the memory device includes forming the control gate within a trench formed in a semiconductor substrate, and forming charge storing regions in the semiconductor substrate on both sides of the control gate in a self-aligning manner, thereby allowing for multi-level cell operation.

摘要翻译： 在具有埋地控制栅极的非易失性存储器件中，增加控制栅极的有效沟道长度以限制穿通，并且增加用于存储电荷的区域以获得有利的大容量。 一种制造存储器件的方法包括：在形成于半导体衬底中的沟槽内形成控制栅极，并以自对准的方式在控制栅极两侧的半导体衬底中形成电荷存储区域，从而允许多级 电池操作。

公开(公告)号：US07416941B2

公开(公告)日：2008-08-26

申请号：US11426623

申请日：2006-06-27

申请人： Brent A. Anderson ,  William F. Clark, Jr. ,  Edward J. Nowak

发明人： Brent A. Anderson ,  William F. Clark, Jr. ,  Edward J. Nowak

IPC分类号： H01L21/8247

CPC分类号： H01L29/785 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66795 ,  H01L29/7887 ,  Y10S438/954

摘要： A four-bit FinFET memory cell, a method of fabricating a four-bit FinFET memory cell and an NVRAM formed of four-bit FINFET memory cells. The four-bit memory cell including two charge storage regions in opposite ends of a dielectric layer on a first sidewall of a fin of a FinFET and two additional charge storage regions in opposite ends of a dielectric layer on a second sidewall of the fin of the FinFET, the first and second sidewalls being opposite one another.

摘要翻译： 四位FinFET存储单元，制造四位FinFET存储单元的方法和由四位FINFET存储单元形成的NVRAM。 该四位存储单元包括在FinFET的鳍的第一侧壁上的电介质层的相对端中的两个电荷存储区，以及位于鳍的翅片的第二侧壁上的电介质层的相对端中的两个附加电荷存储区 FinFET，第一和第二侧壁彼此相对。

公开(公告)号：US20080099832A1

公开(公告)日：2008-05-01

申请号：US11979183

申请日：2007-10-31

申请人： Boaz Eitan

发明人： Boaz Eitan

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L21/3143 ,  H01L21/32 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11517 ,  H01L29/792 ,  Y10S438/954

摘要： A method of fabricating an oxide-nitride-oxide (ONO) layer in a memory cell to retain charge well in the nitride layer includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer and oxidizing a top oxide layer, thereby causing oxygen to be introduced into the nitride layer. Another method includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer and oxidizing a portion of a top oxide layer, thereby causing oxygen to be introduced into the nitride layer and depositing a remaining portion of the top oxide layer, thereby assisting in controlling the amount of oxygen introduced into the nitride layer. A further method includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer, depositing a portion of a top oxide layer and oxidizing a remaining portion of the top oxide layer, thereby causing oxygen to be introduced into the nitride layer.

摘要翻译： 在存储单元中制造氧化物 - 氮化物 - 氧化物（ONO）层以在氮化物层中保持电荷的方法包括以下步骤：在衬底上形成底部氧化物层，沉积氮化物层和氧化顶部氧化物层; 从而导致氧气被引入到氮化物层中。 另一种方法包括以下步骤：在衬底上形成底部氧化物层，沉积氮化物层并氧化顶部氧化物层的一部分，从而使氧被引入到氮化物层中并沉积顶部氧化物层的剩余部分， 从而有助于控制引入到氮化物层中的氧的量。 另一种方法包括以下步骤：在衬底上形成底部氧化物层，沉积氮化物层，沉积顶部氧化物层的一部分并氧化顶部氧化物层的剩余部分，从而将氧气引入氮化物层 。

公开(公告)号：US20080079063A1

公开(公告)日：2008-04-03

申请号：US11931586

申请日：2007-10-31

申请人： S. HERNER

发明人： S. HERNER

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11578 ,  H01L27/1203 ,  Y10S438/954

摘要： A bottom-gate thin film transistor having a silicide gate is described. This transistor is advantageously formed as SONOS-type nonvolatile memory cell, and methods are described to efficiently and robustly form a monolithic three dimensional memory array of such cells. The fabrication methods described avoid photolithography over topography and difficult stack etches of prior art monolithic three dimensional memory arrays of charge storage devices. The use of a silicide gate rather than a polysilicon gate allows increased capacitance across the gate oxide.

摘要翻译： 描述了具有硅化物栅极的底栅薄膜晶体管。 该晶体管有利地形成为SONOS型非易失性存储单元，并且描述了有效且鲁棒地形成这种单元的单片三维存储器阵列的方法。 所描述的制造方法避免了对现有技术的电荷存储装置的单片三维存储阵列的地形和难以堆叠蚀刻的光刻。 使用硅化物栅极而不是多晶硅栅极允许跨越栅极氧化物的电容增加。

公开(公告)号：US07288452B2

公开(公告)日：2007-10-30

申请号：US11024740

申请日：2004-12-30

申请人： Kae Hoon Lee

发明人： Kae Hoon Lee

IPC分类号： H01L21/8234 ,  H01L21/8242

CPC分类号： H01L27/11568 ,  H01L27/115 ,  Y10S438/954

摘要： A method of manufacturing a semiconductor device including forming an ONO film on a semiconductor substrate and a hard mask layer on the ONO film, forming a trench by etching the hard mask layer and the ONO film on a field region of the semiconductor substrate using a photo etch process and etching the field region of the semiconductor substrate, and forming a device separator at the trench. The method also includes exposing the ONO film by removing the hard mask layer on the ONO film, and leaving the ONO film only on a prospective SONOS gate in a cell region of the semiconductor substrate and removing the ONO film the remainder region thereof. The method further includes forming a gate oxide film on the semiconductor substrate at an outside of the ONO film, and forming a gate electrode on the gate oxide film and the ONO film, respectively.

摘要翻译： 一种制造半导体器件的方法，包括在ONO膜上的半导体衬底和硬掩模层上形成ONO膜，通过使用照片在半导体衬底的场区域上蚀刻硬掩模层和ONO膜来形成沟槽 蚀刻工艺并蚀刻半导体衬底的场区域，以及在沟槽处形成器件隔离器。 该方法还包括通过去除ONO膜上的硬掩模层来暴露ONO膜，并且仅将ONO膜留在半导体衬底的单元区域中的预期SONOS栅极上，并将ONO膜的剩余区域除去。 该方法还包括在ONO膜的外部在半导体衬底上形成栅极氧化膜，并在栅极氧化物膜和ONO膜上分别形成栅电极。

公开(公告)号：US20070212841A1

公开(公告)日：2007-09-13

申请号：US11602809

申请日：2006-11-21

申请人： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

发明人： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/4983 ,  H01L21/28282 ,  H01L21/823828 ,  H01L21/823864 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/792 ,  H01L29/7923 ,  Y10S438/954

摘要： A gate stack is formed on a substrate. The gate stack has a sidewall. An oxide-nitride-oxide material is deposited on the gate stack. Portions of the oxide-nitride-oxide material are removed to form an oxide-nitride-oxide structure. The oxide-nitride-oxide structure has a generally L-shaped cross-section with a vertical portion along at least part of the gate stack sidewall and a horizontal portion along the substrate. A top oxide material is deposited over the substrate. A silicon nitride spacer material is deposited over the top oxide material. Portions of the top oxide material and the silicon nitride spacer material are removed to form a silicon nitride spacer separated from the oxide-nitride-oxide stack by the top oxide material. Source/drain regions are formed in the substrate.

摘要翻译： 栅极堆叠形成在基板上。 栅极堆叠具有侧壁。 氧化物 - 氮化物 - 氧化物材料沉积在栅极叠层上。 除去氧化物 - 氮化物 - 氧化物材料的一部分以形成氧化物 - 氧化物 - 氧化物结构。 氧化物 - 氧化物 - 氧化物结构具有通常为L形的横截面，沿着栅极叠层侧壁的至少一部分和沿着衬底的水平部分具有垂直部分。 顶部氧化物材料沉积在衬底上。 在顶部氧化物材料上沉积氮化硅间隔物材料。 除去顶部氧化物材料和氮化硅间隔物材料的部分以形成通过顶部氧化物材料从氧化物 - 氮化物 - 氧化物堆叠体分离的氮化硅间隔物。 源极/漏极区域形成在衬底中。

公开(公告)号：US20070161169A1

公开(公告)日：2007-07-12

申请号：US11306710

申请日：2006-01-09

申请人： Michael P. Belyansky ,  Dureseti Chidambarrao ,  Oleg Gluschenkov

发明人： Michael P. Belyansky ,  Dureseti Chidambarrao ,  Oleg Gluschenkov

IPC分类号： H01L21/8234

CPC分类号： H01L29/0653 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/78609 ,  Y10S438/954

摘要： A field effect transistor (FET) device includes a gate conductor and gate dielectric formed over an active device area of a semiconductor substrate. A drain region is formed in the active device area of the semiconductor substrate, on one side of the gate conductor, and a source region is formed in the active device area of the semiconductor substrate, on an opposite side of the gate conductor. A dielectric halo or plug is formed in the active area of said semiconductor substrate, the dielectric halo or plug disposed in contact between the drain region and a body region, and in contact between the source region and the body region.

摘要翻译： 场效应晶体管（FET）器件包括在半导体衬底的有源器件区域上形成的栅极导体和栅极电介质。 在半导体衬底的有源器件区域中，在栅极导体的一侧上形成漏极区域，并且在栅极导体的相对侧上在半导体衬底的有源器件区域中形成源极区域。 在所述半导体衬底的有源区域中形成介电晕或插塞，所述介电晕或插头设置在所述漏区和体区之间并且在所述源区与所述体区之间接触。

公开(公告)号：US20070117353A1

公开(公告)日：2007-05-24

申请号：US11625177

申请日：2007-01-19

申请人： Chih Hao Wang ,  Hsin-Huei Chen ,  Chong-Jen Huang ,  Kuang-Wen Liu ,  Jia-Rong Chiou ,  Chong-Mu Chen

发明人： Chih Hao Wang ,  Hsin-Huei Chen ,  Chong-Jen Huang ,  Kuang-Wen Liu ,  Jia-Rong Chiou ,  Chong-Mu Chen

IPC分类号： H01L29/94 ,  H01L21/326

CPC分类号： H01L21/022 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28282 ,  H01L21/3144 ,  H01L29/66833 ,  Y10S438/954

摘要： A semiconductor device having a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure is formed by providing a first silicon oxide layer and a silicon nitride layer over a substrate having a memory region and a logic device region; patterning the first silicon oxide layer and the silicon nitride layer to define bottom oxide and silicon nitride portions of partially completed ONO stacks and to expose the substrate in the logic device regions; performing a rapid thermal annealing process in the presence of a radical oxidizing agent to form concurrently a second silicon oxide layer on the exposed surface of the silicon nitride layer and a gate oxide layer over the substrate; and depositing a conductive layer over the completed ONO stacks and the gate oxide. The invention is employed in manufacture of, for example, memory devices having and peripheral logic devices and memory cells including ONO structures. Exposing the patterned silicon nitride to the oxygen radical during the RTO according to the invention significantly reduces the processing time, and reduces the thermal budget. Moreover, because according to the invention the upper surface and the sidewalls of the silicon nitride layer are covered by the top oxide layer, the silicon nitride is not exposed during a subsequent cleaning process. As a result of increased contact area between the polysilicon gate and the top oxide layer, the coupling ratio of the gate is increased.

摘要翻译： 通过在具有存储区域和逻辑器件区域的衬底上提供第一氧化硅层和氮化硅层来形成具有氧化硅/氮化硅/氧化硅（“ONO”）结构的半导体器件; 图案化第一氧化硅层和氮化硅层以限定部分完成的ONO堆叠的底部氧化物和氮化硅部分并且暴露逻辑器件区域中的衬底; 在自由基氧化剂的存在下进行快速热退火工艺，以在氮化硅层的暴露表面和衬底上的栅氧化层上同时形成第二氧化硅层; 以及在完成的ONO堆叠和栅极氧化物上沉积导电层。 本发明用于制造例如具有外围逻辑器件的存储器件和包括ONO结构的存储器单元。 根据本发明，在RTO期间将图案化的氮化硅暴露于氧自由基显着减少了处理时间，并降低了热预算。 此外，由于根据本发明，氮化硅层的上表面和侧壁被顶部氧化物层覆盖，所以在随后的清洁过程中氮化硅不暴露。 由于多晶硅栅极和顶部氧化物层之间的接触面积增加，栅极的耦合比增加。