公开(公告)号：US20060211179A1

公开(公告)日：2006-09-21

申请号：US11364891

申请日：2006-02-28

申请人： Ralf Siemieniec ,  Hans-Joachim Schulze

发明人： Ralf Siemieniec ,  Hans-Joachim Schulze

IPC分类号： H01L21/332

CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/7805

摘要： The invention relates to a semiconductor component, which comprises a semiconductor body having a first and a second terminal zone of a first conduction type (n), a channel zone of a second conduction type (p), which is short circuited with the second terminal zone, a drift zone of the first conduction type (n) with weaker doping than the terminal zones, which drift zone is formed between the channel zone and the first terminal zone, the channel zone being formed between the drift zone and the second terminal zone, a control electrode, formed so that it is insulated from the channel zone, for controlling a conductive channel in the channel zone between the second terminal zone and the drift zone, and is distinguished in that a field stop zone of the first conduction type (n) is formed between the first terminal zone and the drift zone, the field stop zone having heavier doping than the drift zone and weaker doping than the first terminal zone, the maximum doping of the field stop zone being at most a factor of about 102 heavier than the doping of the drift zone.

摘要翻译： 本发明涉及一种半导体元件，其包括具有第一导电类型（n）的第一和第二端子区，与第二端子短路的第二导电类型（p）的沟道区的半导体本体 区域，具有比端子区域弱的掺杂的第一导电类型（n）的漂移区，在沟道区和第一端区之间形成漂移区，沟道区形成在漂移区和第二端区之间 形成为与沟道区绝缘的控制电极，用于控制第二端子区与漂移区之间的沟道区中的导电沟道，其特征在于，第一导电类型的场阻挡区 n）形成在第一末端区域和漂移区域之间，场停止区域具有比漂移区更重的掺杂和比第一末端区域更弱的掺杂，场停止区域的最大掺杂 至多比漂移区的掺杂重约10倍。

公开(公告)号：US20060197164A1

公开(公告)日：2006-09-07

申请号：US11408133

申请日：2006-04-20

申请人： Nick Lindert ,  Anand Murthy ,  Justin Brask

发明人： Nick Lindert ,  Anand Murthy ,  Justin Brask

IPC分类号： H01L29/76 ,  H01L21/332

CPC分类号： H01L29/66628 ,  H01L29/66636

摘要： An epitaxially deposited source/drain extension may be formed for a metal oxide semiconductor field effect transistor. A sacrificial layer may be formed and etched away to undercut under the gate electrode. Then a source/drain extension of epitaxial silicon may be deposited to extend under the edges of the gate electrode. As a result, the extent by which the source/drain extension extends under the gate may be controlled by controlling the etching of the sacrificial material. Its thickness and depth may be controlled by controlling the deposition process. Moreover, the characteristics of the source/drain extension may be controlled independently of those of the subsequently formed deep or heavily doped source/drain junction.

公开(公告)号：US20060068552A1

公开(公告)日：2006-03-30

申请号：US11233637

申请日：2005-09-23

申请人： Takashi Ogura

发明人： Takashi Ogura

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/332

CPC分类号： H01L29/0878 ,  H01L21/76213 ,  H01L21/823481 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66681 ,  H01L29/7816

摘要： In a semiconductor device manufacturing method of the present invention, a polysilicon film and a silicon nitride film are deposited on an upper surface of an epitaxial layer. Patterning is performed so that the polysilicon film and the silicon nitride film are left in regions in which a LOCOS oxide film is to be formed. Then, using steps of the polysilicon film and the silicon nitride film as alignment marks, a diffusion layer as drain regions is formed. Subsequently, the LOCOS oxide film is formed. This manufacturing method enables the diffusion layer to be formed with high position accuracy without being affected by a shape of the LOCOS oxide film.

公开(公告)号：US06998298B1

公开(公告)日：2006-02-14

申请号：US10639058

申请日：2003-08-11

申请人： Andrew E. Horch

发明人： Andrew E. Horch

IPC分类号： H01L21/332

CPC分类号： H01L29/7408 ,  H01L29/7436

摘要： A thyristor memory device may comprise a capacitor electrode formed over a base region of the thyristor using a replacement gate process. During formation of the thyristor, a base-emitter boundary may be aligned relative to a shoulder of the capacitor electrode. In a particular embodiment, the replacement gate process may comprise defining a trench in a layer of dielectric over semiconductor material. Conductive material for the electrode may be formed over the dielectric and in the trench. It may further be patterned to form a shoulder for the electrode that extends over regions of the dielectric over a base region for the thyristor. The extent of the shoulder may be used to pattern the dielectric and/or to assist alignment of implants for the base and emitter regions of the thyristor.

摘要翻译： 晶闸管存储器件可以包括使用替换栅极工艺在晶闸管的基极区域上形成的电容器电极。 在晶闸管的形成期间，基极 - 发射极边界可以相对于电容器电极的台肩对准。 在特定实施例中，替换栅极工艺可以包括在半导体材料上的介电层中限定沟槽。 用于电极的导电材料可以形成在电介质和沟槽中。 可以进一步图案化以形成电极的肩部，该电极在用于晶闸管的基极区域上的电介质的区域上延伸。 可以使用肩部的程度来图案化电介质和/或辅助晶闸管的基极和发射极区域的植入物的对准。

公开(公告)号：US06979602B1

公开(公告)日：2005-12-27

申请号：US10730755

申请日：2003-12-08

申请人： Andrew Horch ,  Scott Robins

发明人： Andrew Horch ,  Scott Robins

IPC分类号： H01L21/762 ,  H01L27/08 ,  H01L29/74 ,  H01L21/332

CPC分类号： H01L21/76224 ,  H01L27/0817 ,  H01L29/74

摘要： A semiconductor device is formed including a substrate having an upper surface, a thyristor region in the substrate and a control port adapted for capacitively coupling to at least a portion of the thyristor region via a dielectric material. According to an example embodiment of the present invention, a trench is formed in the substrate and subsequently filled with materials including dielectric material and a control port. The control port is adapted for capacitively coupling to the thyristor via the dielectric material for controlling current flow in the thyristor (e.g., for causing an outflow of minority carriers from a portion of the thyristor for switching the thyristor from conducting state to a blocking state). A portion of the substrate adjacent to the upper surface is implanted with a species of ions, and the dielectric material via which the control port capacitively couples to the thyristor does not include the species of ions. In one implementation, a filled portion of the trench over the control port inhibits ions from implanting the dielectric material. In another implementation, the control port is formed recessed, relative to the upper surface of the substrate, such that the ion implant depth of the region adjacent to the upper surface is shallower than the recessed control port. With this approach, current control in the thyristor is effected using an arrangement that inhibits ion implantation damage to dielectric material used for controlling current in the thyristor.

摘要翻译： 形成半导体器件，其包括具有上表面的衬底，衬底中的晶闸管区域和适于经由电介质材料电容耦合到晶闸管区域的至少一部分的控制端口。 根据本发明的示例性实施例，在衬底中形成沟槽，随后填充包括电介质材料和控制端口的材料。 控制端口适于通过用于控制晶闸管中的电流的电介质材料电容耦合到晶闸管（例如，用于使晶闸管的一部分的少数载流子流出，将晶闸管从导通状态切换到阻塞状态） 。 与上表面相邻的衬底的一部分注入一些离子，并且电容耦合到晶闸管的电介质材料不包括离子种类。 在一个实施方案中，控制端口上的沟槽的填充部分抑制离子注入电介质材料。 在另一实施方案中，控制端口相对于衬底的上表面形成为凹陷，使得与上表面相邻的区域的离子注入深度比凹入的控制端口浅。 采用这种方法，晶闸管的电流控制是通过抑制用于控制晶闸管中的电流的电介质材料的离子注入损伤的装置实现的。

公开(公告)号：US06927101B2

公开(公告)日：2005-08-09

申请号：US10402812

申请日：2003-03-28

申请人： Ralf Henninger ,  Franz Hirler ,  Martin Pölzl ,  Walter Rieger

发明人： Ralf Henninger ,  Franz Hirler ,  Martin Pölzl ,  Walter Rieger

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L21/332

CPC分类号： H01L29/7813 ,  H01L21/2257 ,  H01L21/26586 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/456

摘要： A method for fabricating a field-effect-controllable semiconductor component includes providing a configuration having a semiconductor body with a front side, a rear side, a first terminal zone of a first conduction type, a channel zone of a second conduction type formed above the first terminal zone, and at least one control electrode adjacent the channel zone. The control electrode is insulated from the semiconductor body. A second terminal zone of the first conduction type is fabricated in the channel zone near the front side of the semiconductor body by: doping the channel zone near the front side with a first dopant concentration to fabricate a first zone of the first conduction type, and doping a section of the first zone with a second dopant concentration higher than the first dopant concentration to form a second zone of the first conduction type.

摘要翻译： 一种场效应可控半导体元件的制造方法，其特征在于，具有：具有前侧，后侧，第一导电型的第一端子区，第二导电型的沟道区， 第一端子区和与通道区相邻的至少一个控制电极。 控制电极与半导体本体绝缘。 第一导电类型的第二端子区通过以第一掺杂剂浓度掺杂前面附近的沟道区，制造在第一导电类型的第一区，在靠近半导体本体的前侧的沟道区中制造，以及 以高于第一掺杂剂浓度的第二掺杂剂浓度掺杂第一区的一部分，以形成第一导电类型的第二区。

公开(公告)号：US20050133869A1

公开(公告)日：2005-06-23

申请号：US10709307

申请日：2004-04-28

申请人： Ming-Dou Ker ,  Kuo-Chun Hsu

发明人： Ming-Dou Ker ,  Kuo-Chun Hsu

IPC分类号： H01L27/02 ,  H01L29/74 ,  H01L21/332

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： A double-triggered silicon controller rectifier (SCR) comprises a plurality of N+ diffusion areas, a plurality of P+ diffusion areas, a first N-well region, a second N-well region and a third N-well region formed in a P-substrate. The N+ diffusion areas and the P+ diffusion areas are isolated by shallow trench isolation (STI) structures. Two of the N+ diffusion areas are N-type trigger terminals. Two of the P+ diffusion areas are the P-type trigger terminal.

摘要翻译： 双触发硅控制器整流器（SCR）包括多个N +扩散区域，多个P +扩散区域，第一N阱区域，第二N阱区域和形成在P- 基质。 通过浅沟槽隔离（STI）结构隔离N +扩散区域和P +扩散区域。 N +扩散区域中的两个是N型触发端子。 P +扩散区域中的两个是P型触发端子。

公开(公告)号：US06909107B2

公开(公告)日：2005-06-21

申请号：US10831785

申请日：2004-04-26

申请人： John C. Rodgers ,  Jon D. Maimon

发明人： John C. Rodgers ,  Jon D. Maimon

IPC分类号： H01L21/768 ,  H01L45/00 ,  H01L47/00 ,  H01L21/00 ,  H01L21/06 ,  H01L21/332

CPC分类号： H01L21/76805 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1273 ,  H01L45/16

摘要： A method for manufacturing sidewall contacts for a chalcogenide memory device is disclosed. A first conductive layer is initially deposited on top of a first oxide layer. The first conductive layer is then patterned and etched using well-known processes. Next, a second oxide layer is deposited on top of the first conductive layer and the first oxide layer. An opening is then etched into at least the first oxide layer such that a portion of the first conductive layer is exposed within the opening. The exposed portion of the first conductive layer is then removed from the opening such that the first conductive layer is flush with an inner surface or sidewall of the opening. After depositing a chalcogenide layer on top of the second oxide layer, filling the opening with chalcogenide, a second conductive layer is deposited on top of the chalcogenide layer.

摘要翻译： 公开了一种用于制造硫族化物存储器件的侧壁接触件的方法。 第一导电层最初沉积在第一氧化物层的顶部。 然后使用众所周知的方法对第一导电层进行构图和蚀刻。 接下来，在第一导电层和第一氧化物层的顶部上沉积第二氧化物层。 然后将至少第一氧化物层蚀刻开口，使得第一导电层的一部分暴露在开口内。 然后将第一导电层的暴露部分从开口移除，使得第一导电层与开口的内表面或侧壁齐平。 在第二氧化物层的顶部上沉积硫族化物层之后，用硫族化物填充该开口，在硫族化物层的顶部上沉积第二导电层。

公开(公告)号：US06872602B1

公开(公告)日：2005-03-29

申请号：US10785166

申请日：2004-02-23

申请人： Farid Nemati ,  Badredin Fatemizadeh ,  Andrew Horch ,  Scott Robins

发明人： Farid Nemati ,  Badredin Fatemizadeh ,  Andrew Horch ,  Scott Robins

IPC分类号： H01L21/8242 ,  H01L21/8244 ,  H01L27/08 ,  H01L27/108 ,  H01L27/11 ,  H01L29/417 ,  H01L29/74 ,  H01L21/332

CPC分类号： H01L29/41716 ,  H01L27/0817 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/11 ,  H01L29/74

摘要： Switching times of a thyristor-based semiconductor device are improved by enhancing carrier drainage from a buried thyristor-emitter region. According to an example embodiment of the present invention, a conductive contact extends to a doped well region buried in a substrate and is adapted to drain carriers therefrom. The device includes a thyristor body having at least one doped emitter region buried in the doped well region. A conductive thyristor control port is adapted to capacitively couple to the thyristor body and to control current flow therein. With this approach, the thyristor can be rapidly switched between resistance states, which has been found to be particularly useful in high-speed data latching implementations including but not limited to memory cell applications.

摘要翻译： 通过增强从掩埋晶闸管 - 发射极区域的载流子排放，可以改善晶闸管基半导体器件的开关时间。 根据本发明的示例性实施例，导电接触延伸到掩埋在衬底中的掺杂阱区，并且适于从其引出载流子。 该器件包括晶体管本体，其具有埋在掺杂阱区中的至少一个掺杂射极区。 导电晶闸管控制端口适于电容耦合到晶闸管主体并控制其中的电流。 通过这种方法，晶闸管可以在电阻状态之间快速切换，这已经被发现在包括但不限于存储器单元应用的高速数据锁存实现中特别有用。

公开(公告)号：US20050023591A1

公开(公告)日：2005-02-03

申请号：US10632186

申请日：2003-07-30

申请人： Yi Ding

发明人： Yi Ding

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L21/332 ,  H01L21/336 ,  H01L29/76

CPC分类号： H01L27/11526 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/7887

摘要： In a nonvolatile memory cell having at least two floating gates, each floating gate (160) has an upward protruding portion. This portion can be formed as a spacer over a sidewall of the select gate (140). The spacer can be formed from a layer (160.2) deposited after the layer (160.1) which provides a lower portion of the floating gate. Alternatively, the upward protruding portion and the lower portion can be formed from the same layers or sub-layers all of which are present in both portions. The control gate (170) can be defined without photolithography. Other embodiments are also provided.

摘要翻译： 在具有至少两个浮动栅极的非易失性存储单元中，每个浮动栅极（160）具有向上突出部分。 该部分可以形成为在选择门（140）的侧壁上的间隔物。 隔离物可以由沉积在提供浮动栅极的下部的层（160.1）之后的层（160.2）形成。 或者，向上突出部分和下部分可以由相同的层或子层形成，所有这些层或子层都存在于两个部分中。 控制栅极（170）可以在没有光刻的情况下被定义。 还提供了其他实施例。