公开(公告)号：US20240250155A1

公开(公告)日：2024-07-25

申请号：US18590179

申请日：2024-02-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： I-Hsieh Wong ,  Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/66818 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/785 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31111

摘要： In an embodiment, a method includes: forming a fin extending from a substrate, the fin having a first width and a first height after the forming; forming a dummy gate stack over a channel region of the fin; growing an epitaxial source/drain in the fin adjacent the channel region; and after growing the epitaxial source/drain, replacing the dummy gate stack with a metal gate stack, the channel region of the fin having the first width and the first height before the replacing, the channel region of the fin having a second width and a second height after the replacing, the second width being less than the first width, the second height being less than the first height.

公开(公告)号：US20240250150A1

公开(公告)日：2024-07-25

申请号：US18443994

申请日：2024-02-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sheng-Liang Pan ,  Chen Yung Tzu ,  Chung-Chieh Lee ,  Yung-Chang Hsu ,  Hung Chia-Yang ,  Po-Chuan Wang ,  Guan-Xuan Chen ,  Huan-Just Lin

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/6656 ,  H01L21/02126 ,  H01L21/0217 ,  H01L29/0847 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

摘要： A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.

公开(公告)号：US20240250119A1

公开(公告)日：2024-07-25

申请号：US18356851

申请日：2023-07-21

申请人： SANDISK TECHNOLOGIES LLC

发明人： Masashi ISHIDA

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/66

CPC分类号： H01L29/0634 ,  H01L29/0661 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/66659 ,  H01L29/66689

摘要： A field effect transistor includes a semiconductor channel having a doping of a first conductivity type, a gate structure overlying the semiconductor channel, a source region and a drain region, a source-side extension region including a source-side-extension plate portion and source-side-extension rail portions that overlie the source-side-extension plate portion, source-side counter-doped rails having a doping of the first conductivity type, a drain-side extension region including a drain-side-extension plate portion and drain-side-extension rail portions that overlie the drain-side-extension plate portion, and drain-side counter-doped rails interlaced with the drain-side-extension rail portions. A first superjunction structure is provided between the source-side counter-doped rails and the source-side extension region. A second superjunction structure is provided between the drain-side counter-doped rails and the drain-side extension region.

公开(公告)号：US20240249981A1

公开(公告)日：2024-07-25

申请号：US18594735

申请日：2024-03-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuei-Ming Chang ,  Rei-Jay Hsieh ,  Cheng-Han Wu ,  Chie-luan Lin

IPC分类号： H01L21/8238 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823878 ,  H01L21/76232 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7848

摘要： A device includes a first transistor, a second transistor, and a dielectric structure. The first transistor is over a substrate and has a first gate structure. The second transistor is over the substrate and has a second gate structure. The dielectric structure is between the first gate structure and the second gate structure. The dielectric structure has a width increasing from a bottom position of the dielectric structure to a first position higher than the bottom position of the dielectric structure. A width of the first gate structure is less than the width of the dielectric structure at the first position.

公开(公告)号：US12046664B2

公开(公告)日：2024-07-23

申请号：US18286152

申请日：2022-05-20

申请人： WUXI CHINA RESOURCES HUAJING MICROELECTRONICS CO., LTD.

发明人： Pengfei Jia ,  Qiang Rui ,  Wei Li

IPC分类号： H01L29/739 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66

CPC分类号： H01L29/7396 ,  H01L29/0856 ,  H01L29/452 ,  H01L29/66333

摘要： A vertical semiconductor structure with an integrated sampling structure and a method for manufacturing the same; the vertical semiconductor structure includes a vertical-semiconductor-structure unit cell, a sampling unit cell, a control electrode, a first electrode, a second electrode, and a sampling electrode. The sampling electrode performs real-time sampling of a voltage difference between the first electrode and the second electrode; a PN junction is formed between a first/second P-type diffusion region and a second N-type base region, which forms a potential barrier blocking electron emission from the sampling electrode. Therefore, a voltage signal of the sampling electrode is input into a protection circuit, which detects whether the vertical-semiconductor-structure unit cell is desaturated when it determines that the unit cell is in the open state. Second, a sampling resistor is connected between the sampling electrode and the first electrode to ensure the stable operation of the sampling unit cell.

公开(公告)号：US12046636B2

公开(公告)日：2024-07-23

申请号：US17880839

申请日：2022-08-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shahaji B. More

IPC分类号： H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

摘要： The present disclosure relates an integrated chip. The integrated chip may include a semiconductor substrate having sidewalls that define a plurality of fins. A dielectric material is arranged between the plurality of fins and a gate structure is disposed over the dielectric material and around the plurality of fins. Epitaxial source/drain regions are disposed along opposing sides of the gate structure and respectively include a plurality of source/drain segments disposed on the plurality of fins and a doped epitaxial material disposed onto and between the plurality of source/drain segments. A first source/drain segment of the plurality of source/drain segments laterally extends in opposing directions to different distances past opposing sides of an underlying first fin of the plurality of fins.

公开(公告)号：US12046632B2

公开(公告)日：2024-07-23

申请号：US18182893

申请日：2023-03-13

申请人： Samsung Electronics Co., Ltd.

发明人： Haejun Yu ,  Kyungin Choi ,  Seung Hun Lee

IPC分类号： H01L29/06 ,  B82Y10/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/0653 ,  H01L29/42392 ,  H01L29/4991 ,  H01L29/66553 ,  H01L27/092

摘要： A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, the channel pattern including semiconductor patterns stacked and spaced apart from each other, a gate electrode extending across the channel pattern, and inner spacers between the gate electrode and the source/drain pattern. The semiconductor patterns include stacked first and second semiconductor patterns. The gate electrode includes first and second portions, which are sequentially stacked between the substrate and the first and second semiconductor patterns, respectively. The inner spacers include first and second air gaps, between the first and second portions of the gate electrode and the source/drain pattern. The largest width of the first air gap is larger than that of the second air gap.

公开(公告)号：US12046599B2

公开(公告)日：2024-07-23

申请号：US17522051

申请日：2021-11-09

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Cheol Kim ,  Jongchul Park ,  Hyunho Jung

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L27/0924 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5286 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

摘要： A semiconductor device includes a substrate having first and second active regions. A first active pattern is on the first active region and includes first source/drain patterns and a first channel pattern therebetween. A second active pattern is on the second active region and includes second source/drain patterns and a second channel pattern therebetween. A gate electrode includes a first gate electrode on the first channel pattern and a second gate electrode on the second channel pattern. A gate cutting pattern is between the first and second gate electrodes and separates the first and second gate electrodes from each other. A pair of gate spacers is on opposite sidewalls of the first gate electrode extending along opposite sidewalls of the gate cutting pattern towards the second gate electrode. The gate cutting pattern includes first to third parts having maximum widths that increase from the first to the third part.

公开(公告)号：US20240243203A1

公开(公告)日：2024-07-18

申请号：US18622659

申请日：2024-03-29

申请人： Intel Corporation

发明人： Biswajeet GUHA ,  William HSU ,  Leonard P. GULER ,  Dax M. CRUM ,  Tahir GHANI

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

CPC分类号： H01L29/7856 ,  H01L21/02603 ,  H01L21/823481 ,  H01L23/5226 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/42392 ,  H01L2029/7858

摘要： Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

公开(公告)号：US20240243188A1

公开(公告)日：2024-07-18

申请号：US18513759

申请日：2023-11-20

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Hyohoon BYEON ,  Seokhoon KIM ,  Unki KIM ,  Pankwi PARK ,  Sungkeun LIM ,  Yuyeong JO

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/66545 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： An integrated circuit device includes: a rear wiring structure; an insulating substrate including fin structures disposed on the rear wiring structure and extending in a first horizontal direction; a device isolation layer disposed between the fin structures; a lower insulating layer covering the fin structures; gate structures extending in a second horizontal direction crossing the first horizontal direction; a plurality of nanosheet stacks disposed on the lower insulating layer; a first source/drain region disposed on the insulating substrate and including a body portion and a vertical extension portion, wherein the body portion is disposed between the plurality of nanosheet stacks, and the vertical extension portion passes through the lower insulating layer and through some of the fin structures; a semiconductor epitaxial structure at least partially surrounding the vertical extension portion of the first source/drain region; and a lower contact connecting the semiconductor epitaxial structure with the rear wiring structure.