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    Memory Arrays
    81.
    发明申请
    Memory Arrays 审中-公开

    公开(公告)号：US20190178969A1

    公开(公告)日：2019-06-13

    申请号：US16280588

    申请日：2019-02-20

    申请人： Micron Technology, Inc.

    发明人： Zengtao T. Liu

    IPC分类号： G01R33/58 ,  G11C7/10 ,  G11C5/02 ,  H01L27/24 ,  H01L45/00 ,  G11C13/00 ,  G11C8/14 ,  G11C5/06 ,  G01R33/12

    摘要： Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2 F2.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    82.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20190139979A1

    公开(公告)日：2019-05-09

    申请号：US16018199

    申请日：2018-06-26

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： KOHJI KANAMORI ,  Seo-Goo Kang ,  Younghwan Son ,  Kwonsoon Jo

    IPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  G11C8/14

    CPC分类号： H01L27/11582 ,  G11C8/14 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

    摘要： A three-dimensional semiconductor memory device includes a peripheral logic structure on a semiconductor substrate. A horizontal semiconductor layer is on the peripheral logic structure and includes a cell array region and a connection region. Electrode structures extend in a first direction on the horizontal semiconductor layer and are spaced apart in a second direction intersecting the first direction. A pair of the electrode structures adjacent to each other are symmetrically disposed to define a contact region partially exposing the horizontal semiconductor layer. A through via structure is on the contact region and connects the electrode structures to the peripheral logic structure. Each of the electrode structures includes a plurality of gate insulation regions extending along the first direction on the connection region. The gate insulation regions have different lengths from each other in the first direction.

    STATIC RANDOM ACCESS MEMORY STRUCTURE
    84.
    发明申请
    STATIC RANDOM ACCESS MEMORY STRUCTURE 审中-公开

    公开(公告)号：US20190096892A1

    公开(公告)日：2019-03-28

    申请号：US16162340

    申请日：2018-10-16

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Shu-Ru Wang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chien-Hung Chen ,  Chun-Hsien Huang ,  Li-Ping Huang ,  Chun-Yen Tseng ,  Meng-Ping Chuang

    IPC分类号： H01L27/11 ,  G11C11/412 ,  G11C7/18 ,  G11C8/14 ,  G11C5/06

    摘要： A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise a first fin structure, the PG2A and the PG2B comprise a second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2, the first local interconnection layer and the second local interconnection layer are monolithically formed structures respectively.

    CONNECTIONS FOR MEMORY ELECTRODE LINES
    87.
    发明申请
    CONNECTIONS FOR MEMORY ELECTRODE LINES 审中-公开

    公开(公告)号：US20180374902A1

    公开(公告)日：2018-12-27

    申请号：US16057603

    申请日：2018-08-07

    申请人： Micron Technology, Inc.

    发明人： Hernan A. Castro

    IPC分类号： H01L27/24 ,  H01L45/00 ,  G11C7/18 ,  G11C13/00 ,  G11C8/14

    摘要： Subject matter disclosed herein relates to an integrated circuit device having a socket interconnect region for connecting a plurality of conductive lines at a first vertical level to interconnect structures formed at a second vertical level different from the first vertical level. The conductive lines include a plurality of contacted lines that are vertically connected to the interconnect structures at the socket interconnect region, a plurality of terminating lines terminating at the socket interconnect region, and a plurality of pass-through lines that pass through the socket interconnect region without being vertically connected and without being terminated at the socket interconnect region.

    CONTENT ADDRESSABLE MEMORY AND SEMICONDUCTOR DEVICE
    89.
    发明申请
    CONTENT ADDRESSABLE MEMORY AND SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180350438A1

    公开(公告)日：2018-12-06

    申请号：US15926863

    申请日：2018-03-20

    申请人： Renesas Electronics Corporation

    发明人： Makoto Yabuuchi

    IPC分类号： G11C15/04 ,  G11C8/08 ,  G11C8/14 ,  G11C16/12 ,  G11C11/412

    摘要： An object of the present disclosure is to provide a content addressable memory realizing higher speed of a search access. A content addressable memory includes: a plurality of memory cells; a match line coupled to the plurality of memory cells; a search line coupled to each of the plurality of memory cells; a match line output circuit coupled to the match line; and a potential changing circuit coupled to the match line and changing the potential of the match line.