公开(公告)号：US12131990B2

公开(公告)日：2024-10-29

申请号：US17326846

申请日：2021-05-21

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Fei Zhou

IPC分类号： H01L23/522 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L23/5226 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/28518 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L29/456

摘要： Semiconductor structures and fabrication methods are provided. The semiconductor includes a substrate; a plurality of discrete fins on the substrate; a gate structure on the substrate, and across the plurality of discrete fins by covering portions of sidewall surfaces and top surfaces of the plurality of discrete fins; a plurality of doped source/drain layers in the plurality of discrete fins and at both sides of the gate structure; a conductive layer, formed at one or two sides of the gate structure, connecting multiple doped source/drain layers of the plurality of doped source/drain layers, and with a top surface lower than a top surface of the gate structure; and a conductive plug on the conductive layer and in contact with a portion of a surface of the conductive layer.

公开(公告)号：US12089501B2

公开(公告)日：2024-09-10

申请号：US17029726

申请日：2020-09-23

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Ming Zhou

IPC分类号： H10N50/10 ,  G11C11/16 ,  H01L29/82 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC分类号： H10N50/10 ,  G11C11/16 ,  G11C11/161 ,  H01L29/82 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

摘要： Semiconductor structure and fabrication method are provided. The semiconductor structure includes: a substrate and a magnetic tunnel junction on the substrate. The magnetic tunnel junction includes: a bottom electromagnetic structure on the substrate, an insulating layer on the bottom electromagnetic structure, and a top electromagnetic structure on the insulating layer. The semiconductor structure further includes a sidewall tunneling layer on sidewall surfaces of the magnetic tunnel junction.

公开(公告)号：US20240258238A1

公开(公告)日：2024-08-01

申请号：US18565406

申请日：2021-05-31

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Zengsheng XU ,  Xuezhen JING ,  Hao ZHANG ,  Tiantian ZHANG ,  Hailong YU

IPC分类号： H01L23/532 ,  H01L21/285

CPC分类号： H01L23/53257 ,  H01L21/28568

摘要： A semiconductor structure includes a substrate, a covering layer on the substrate, an auxiliary layer on the covering layer, a first dielectric layer on surfaces of the substrate and the auxiliary layer, and a conductive structure in the first dielectric layer. The semiconductor structure also includes a second dielectric layer on surfaces of the first dielectric layer and the conductive structure, a first opening in the second dielectric layer and the first dielectric layer, and a second opening in the second dielectric layer. The first opening exposes the auxiliary layer, and the second opening exposes the top surface of the conductive structure. A first conductive layer is in the first opening, and a second conductive layer is in the second opening. A growth rate of the first conductive layer over the auxiliary layer is higher than the growth rate of the first conductive layer over the covering layer.

公开(公告)号：US20240186362A1

公开(公告)日：2024-06-06

申请号：US18524910

申请日：2023-11-30

申请人： Semiconductor Manufacturing International (Beijing) Corporation ,  Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Zhanjie LU ,  Zhigao WANG

IPC分类号： H01L27/146

CPC分类号： H01L27/14685 ,  H01L27/14636

摘要： An image sensor and a formation method of the image sensor are provided in the present disclosure. The method includes forming an array substrate, where a photosensitive device is in the array substrate; forming an interconnection structural layer on the array substrate; forming a passivation structural layer on the interconnection structural layer; and forming a connection pad and an isolation wall in the passivation structural layer. The connection pad is electrically connected to the photosensitive device; and the isolation wall is between adjacent photosensitive devices and at least passes through the passivation structural layer and extends to the interconnection structural layer.

公开(公告)号：US11996460B2

公开(公告)日：2024-05-28

申请号：US17470129

申请日：2021-09-09

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Ji Shiliang ,  Xiao Xingyu ,  Zhang Haiyang

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/42392 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/66545 ,  H01L29/78696

摘要： A semiconductor structure and a forming method thereof are provided, where one form of a forming method includes: providing a substrate, where the substrate includes a first region and a second region that are adjacent, stack structures are formed on the first region and the second region, and the stack structures of the first region and the second region and the substrate form a first opening; forming first dielectric layers on a bottom surface and side walls of the first opening, where a second opening is provided between the first dielectric layers; forming a second dielectric layer in the second opening; forming a source/drain doped layer; removing the first dielectric layer between the source/drain doped layer and the second dielectric layer, and forming a groove exposing a side wall, which is close to the second dielectric layer, of the source/drain doped layer; and forming a contact plug in the groove. In the embodiments of the present disclosure, the contact plug is in contact with a top surface of the source/drain doped layer as well as the side walls, which are close to the second dielectric layer and away from the second dielectric layer respectively, of the source/drain doped layer, so that a contact resistance between the contact plug and the source/drain doped layer is relatively small, thereby improving the electrical performance of the semiconductor structure.

公开(公告)号：US11943918B2

公开(公告)日：2024-03-26

申请号：US18135552

申请日：2023-04-17

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Liang Han ,  Hai Ying Wang

IPC分类号： H10B41/30 ,  H01L29/49 ,  H10B41/60

CPC分类号： H10B41/30 ,  H01L29/4933 ,  H10B41/60

摘要： A memory structure is provided in the present disclosure. The memory structure includes a substrate, a plurality of discrete memory gate structures on the substrate where each of the plurality of memory gate structures includes a floating gate layer and a control gate layer on the floating gate layer, an isolation layer formed between adjacent memory gate structures where a top surface of the isolation layer is lower than a top surface of the control gate layer and higher than a bottom surface of the control gate layer, an opening is formed on an exposed sidewall of the control gate layer, and a bottom of the opening is lower than or coplanar with the top surface of the isolation layer, and a metal silicide layer on an exposed surface of the control gate layer and the top surface of the isolation layer.

公开(公告)号：US11908865B2

公开(公告)日：2024-02-20

申请号：US17576876

申请日：2022-01-14

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Da Huang ,  Yao Qi Dong ,  Xiaowan Dai ,  Zhen Tian

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L27/0924 ,  H01L21/823842 ,  H01L21/823878

摘要： A semiconductor structure and a fabrication method of the semiconductor structure are provided. The semiconductor structure includes a substrate. The substrate includes a first region, a second region, and an isolation region between the first region and the second region. The semiconductor structure also includes a first fin, a second fin and a third fin disposed over the first region, the second region, and the isolation region, respectively. Further, the semiconductor structure includes a gate structure. The gate structure includes a first work function layer over the first region and a first portion of the isolation region, and a second work function layer over the second region and a second portion of the isolation region. An interface where the first work function layer is in contact with the second work function layer is located over a top surface of the third fin.

公开(公告)号：US11818874B2

公开(公告)日：2023-11-14

申请号：US17643504

申请日：2021-12-09

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Yong Li

IPC分类号： H01L29/10 ,  H10B10/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49

CPC分类号： H10B10/12 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823892 ,  H01L27/0924 ,  H01L27/0928 ,  H01L29/1083 ,  H01L29/4966

摘要： A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, an interlayer dielectric layer, multiple trenches in the interlayer dielectric layer including first, second, third trenches for forming respective gate structures of first, second, and third transistors, forming an interface layer on the bottom of the trenches; forming a high-k dielectric layer on the interface layer and sidewalls of the trenches; forming a first PMOS work function adjustment layer on the high-k dielectric layer of the third trench; forming a second PMOS work function adjustment layer in the trenches after forming the first PMOS work function adjustment layer; forming an NMOS work function layer in the trenches after forming the second PMOS work function adjustment layer; and forming a barrier layer in the trenches after forming the NMOS work function layer and a metal gate layer on the barrier layer.

公开(公告)号：US11809802B2

公开(公告)日：2023-11-07

申请号：US17198462

申请日：2021-03-11

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Abraham Yoo ,  Ying Jin ,  Jisong Jin

IPC分类号： G06F30/398 ,  H01L21/321 ,  H01L29/40 ,  G06F119/08 ,  G06F119/18

CPC分类号： G06F30/398 ,  H01L21/321 ,  H01L29/401 ,  G06F2119/18

摘要： A process manufacturing method, a method for adjusting a threshold voltage, a device, and a storage medium are provided. One form of a process manufacturing method includes: determining a type of to-be-formed MOS device and a corresponding threshold voltage interval; obtaining, according to a MOS device type and the corresponding threshold voltage interval, a corresponding threshold voltage adjustment process by querying a pre-configured first mapping relationship of the threshold voltage interval and a second mapping relationship of the threshold voltage interval; and establishing a process flow according to the corresponding threshold voltage adjustment process, the first mapping relationship being a mapping relationship between the threshold voltage interval and the MOS device type; and the second mapping relationship being a correspondence between the threshold voltage interval in the first mapping relationship and a threshold voltage adjustment process formed by at least one adjustment process selected from a preset process flow, the threshold voltage adjustment process causing a threshold voltage to be in the corresponding threshold voltage interval under the action of a total threshold voltage offset. According to the present disclosure, the difficulty in adjusting the threshold voltage is reduced.

公开(公告)号：US11770922B2

公开(公告)日：2023-09-26

申请号：US18083894

申请日：2022-12-19

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Fei Zhou

IPC分类号： H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00 ,  H01L21/02 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/8234

CPC分类号： H10B10/12 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/32133 ,  H01L21/7684 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/528 ,  H01L27/0886 ,  H01L29/66545

摘要： Semiconductor device is provided. The semiconductor device includes a base substrate including a first region, a second region, and a third region, a first doped layer in the base substrate at the first region and a second doped layer in the base substrate at the third region, a first gate structure on the base substrate at the second region, a first dielectric layer on the base substrate, a first conductive layer on the first conductive layer and the second doped layer, a second conductive layer on a surface of the first conductive layer, and a third conductive layer on a contact region of the first gate structure. The second region is between the first region and the third region. The contact region is at a top of the first gate structure. A minimum distance between the second conductive layer and the third conductive layer is greater than zero.