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    Magnetic cores with high reluctance differences in flux paths
    3.
    发明授权
    Magnetic cores with high reluctance differences in flux paths 有权

    公开(公告)号：US11532421B2

    公开(公告)日：2022-12-20

    申请号：US17174453

    申请日：2021-02-12

    申请人： International Business Machines Corporation

    发明人： Yuan Yao ,  Todd Edward Takken ,  Andrew Ferencz ,  Xin Zhang ,  Liam Daley McAuliffe

    IPC分类号： H01F27/26 ,  H02M3/335 ,  H01F41/02 ,  H01F1/147 ,  H01F27/28

    摘要： Embodiment of the present invention includes a magnetic structure and a magnetic structure used in a direct current (DC) to DC energy converter. The magnetic structure has an E-core and a plate, with the plate positioned in contact or in near contact with the post surfaces of the E-core. The E-core has a base, a no-winding leg, a transformer leg, and an inductor leg. The no-winding leg, the transformer leg, and the inductor leg are perpendicular and magnetically in contact with the base. The plate is a flat slab with lateral dimensions generally larger than its thickness. The plate has a plate nose that overlaps a top no-winding leg surface of the no-winding leg with a no-winding gap area to form a no-winding gap with a no-winding gap reluctance. The plate also has a plate end that overlaps a top inductor leg surface of the inductor leg with an inductor gap area to form an inductor gap with an inductor gap reluctance. In some embodiments, e.g., where the duty cycle is less than 50 percent, the inductor gap reluctance will be designed to be less than the no-winding gap reluctance. In these cases, the majority of the magnetic flux that passes through the transformer leg will return through the inductor leg, instead of through the no-winding leg. The inductor and no-winding gap reluctances can he adjusted, so that the electromotive force applied to a charge passing through the inductor will partially cancel the electromotive force applied by the transformer secondary. The gap reluctance ratio can be defined, so that the difference in secondary and inductor electromotive forces is equal to the output voltage defined by an optimal no-ripple duty cycle. In this way no changing current is required through the inductor to create a dI/dt inductive voltage drop across the output inductor. Zero output current ripple is achieved.
    Various embodiments of the plate, plate shape, and no-winding leg are disclosed. These embodiments allow achieving a high ratio of no-winding gap reluctance to inductor gap reluctance, for practical, affordable magnetic material structures and aspect ratios. A high gap reluctance ratio enables zero output current ripple for the high transformer turns ratios that are needed to achieve high input to output voltage ratios. The embodiments therefore allow achieving low output current ripple for 48 V or higher input voltages, 1 V or lower output voltages, and high output currents.

    Dual-level pad card edge self-guide and alignment of connector
    5.
    发明授权
    Dual-level pad card edge self-guide and alignment of connector 有权

    公开(公告)号：US11342697B2

    公开(公告)日：2022-05-24

    申请号：US16892426

    申请日：2020-06-04

    申请人： International Business Machines Corporation

    发明人： Paul W Coteus ,  Thomas Cipolla ,  Kyu-hyoun Kim ,  Edmund Blackshear

    IPC分类号： H01R12/72 ,  H05K3/00 ,  H05K1/18 ,  H01R12/70

    摘要： A card, e.g. a printed circuit board (PCB), has one or more conductive layers and one or more non-conductive layers disposed and alternating upon one another to form a stack. One or more of the conductive layers has one or more wiring elements within the conductive layer. The PCB/card has one or more card edges. The PCB also has a plurality of dual-level pad structures on each of one or more of the card edges. The dual-level pad structures each have an upper level, a lower level, and two or more walls. The lower level is a conductive pad with conductive surface. At least one of the conductive pads electrically connects to one or more of the wiring elements and/or one or more vias. In each of the dual-level pad structures, the walls and upper level may be made of an electrically non-conductive, insulating, or dielectric material or may be covered with a conductive material that electrically connects to conductive surface. There are different non-limiting embodiments of the structures and methods of making the structures.

    Stacked nanosheet inverter
    6.
    发明授权
    Stacked nanosheet inverter 有权

    公开(公告)号：US11315923B2

    公开(公告)日：2022-04-26

    申请号：US17023891

    申请日：2020-09-17

    申请人： International Business Machines Corporation

    发明人： Alexander Reznicek ,  Karthik Balakrishnan ,  Bahman Hekmatshoartabari

    IPC分类号： H01L21/02 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

    摘要： A cross-coupled inverter made of nanolayers from a nanosheet stack structure has a left field effect transistor (FET) stack and a right FET stack. The left FET stack has a second left FET stacked on a first left FET. The first and second left FETs have opposite types. The right FET stack has a second right FET stacked on a first right FET. The first and second right FETs have opposite types. The first left and first right FET have a first common source drain (S/D). The left FET stack has a left gate stack surrounding the one or more first left FET channel layers and the one or more second left FET channel layers. The right FET stack has a right gate stack surrounding the one or more first right FET channel layers and the one or more second right FET channel layers. In some embodiments the left/right gate stack has a left/right center gate stack layer and one or more left/right gate stack layers. The center gate stack layers are thicker than the gate stack layers and are between the first and second FETs. The insulating layer surrounds the middle of the center gate stack layers. The first right FET S/D and the second right FET S/D are internally and electrically connected and connected to a Q external connection. The Q external connection is externally connected to the left gate stack. The first left FET S/D and the second left FET S/D are internally, electrically connected together and connected to a QB external connection. The QB external connection is externally connected to the right gate stack.
    During operation, the first common S/D is connected to a first external power contact and the second common S/D is connected to a second external power contact and the Q external connection has a logically opposite value of the QB external connection during a desired operation phase. Chip area is reduced because of the low number of external connections required to wire the cross-coupled inverter device.

    High bandwidth multichip module
    7.
    发明授权
    High bandwidth multichip module 有权

    公开(公告)号：US11315902B2

    公开(公告)日：2022-04-26

    申请号：US16788459

    申请日：2020-02-12

    申请人： International Business Machines Corporation

    发明人： John Knickerbocker

    IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498 ,  H01L23/66 ,  H01L25/18

    摘要： Multi-semiconductor chip modules that have a substrate with a substrate surface, one or more first substrate connections, and one or more second substrate connections. One or more first semiconductor chips (chips) has one or more larger first chip connections and one or more smaller first chip connections on a first chip bottom surface. One or more of the larger first chip connections physically and electrically connected to a respective first substrate connection. One or more second chips has one or more larger second chip connections and one or more smaller second chip connections on a second chip bottom surface. One or more of the larger second chip connections physically and electrically connected to a respective second substrate connection. A bridge has a bridge thickness, a bridge surface, and one or more bridge connections on the bridge surface. A first part of the bridge surface is under the first chip bottom surface and a second part of the bridge surface is under the second chip bottom surface. The bridge is disposed on the substrate between the first semiconductor chip and the second semiconductor chip, and one or more of the smaller first chip connections is physically and electrically connected to a respective first bridge connection on the first part of the bridge surface and one or more of the smaller second chip connection is physically and electrically connected to a respective second bridge connection. Some embodiments, a large surface bridge with the bridge. The large surface bridge and bridge can have different configurations. The bridge thickness allows larger chip connections and smaller connections with high pitch to intermingled in a location within the module. Methods of manufacture are disclosed.