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    INTERCONNECT CHIP AND L-COUPLER FOR MODULAR QUANTUM LINKS
    1.
    发明申请
    INTERCONNECT CHIP AND L-COUPLER FOR MODULAR QUANTUM LINKS 有权

    公开(公告)号：US20240412090A1

    公开(公告)日：2024-12-12

    申请号：US18330680

    申请日：2023-06-07

    Applicant: International Business Machines Corporation

    Inventor： Neereja Sundaresan ,  Shawn Anthony Hall ,  Jason S. Orcutt ,  Jae-Woong Nah ,  Yves Martin ,  Wen-Sen Lu ,  John Michael Cotte

    IPC: G06N10/40

    Abstract: Systems and techniques that facilitate coupling a superconducting cable to a interconnect chip and a quantum processor. In various embodiments, a system can comprise a quantum processor, one or more interconnect chips, and one or more cable connections. The quantum processor can comprise a plurality of qubits. Additionally, the one or more interconnect chips can be bonded to the quantum processor, and the one or more cable connections can be coupled to the one or more interconnect chips. With embodiments, the one or more interconnect chips can comprise one or more signal routings from the one or more cable connections to the quantum processor. Further, in embodiments, a first signal can pass from the one or more cable connections to at least one of the plurality of qubits.

    Method and Apparatus of Processor Wafer Bonding for Wafer-Scale Integrated Supercomputer
    3.
    发明申请
    Method and Apparatus of Processor Wafer Bonding for Wafer-Scale Integrated Supercomputer 有权

    公开(公告)号：US20210351043A1

    公开(公告)日：2021-11-11

    申请号：US16869744

    申请日：2020-05-08

    Applicant: International Business Machines Corporation

    Inventor： Jae-Woong Nah ,  Evan Colgan ,  Robert P. Kuder, II ,  James L. Speidell ,  Bucknell C. Webb

    IPC: H01L21/48 ,  H01L23/473 ,  H01L21/67

    Abstract: A method and apparatus for bonding a processor wafer with a microchannel wafer/glass manifold to form a bonded wafer structure are provided. A glass fixture is also provided for protecting C4 solder bumps on chips disposed on the processor wafer. When the glass fixture is positioned on the processor wafer, posts extending from the glass fixture contact corresponding regions on the processor wafer devoid of C4 solder bumps, so that the glass fixture protects the C4 solder bumps during wafer bonding. The method involves positioning the processor wafer/glass fixture and the microchannel wafer/glass manifold in a metal fixture having one or more alignment structures adapted to engage corresponding alignment elements formed in the processor wafer, glass fixture and/or glass manifold. The metal fixture secures the wafer components in place and, after melting solder pellets disposed between the processor wafer/glass fixture and microchannel wafer/glass manifold, a bonded wafer structure is formed.

    OPTIMIZED STAND-OFFS AND MECHANICAL STOPS FOR PRECISE THREE DIMENSIONAL SELF-ALIGNMENT
    7.
    发明申请
    OPTIMIZED STAND-OFFS AND MECHANICAL STOPS FOR PRECISE THREE DIMENSIONAL SELF-ALIGNMENT 审中-公开

    公开(公告)号：US20190162902A1

    公开(公告)日：2019-05-30

    申请号：US15827306

    申请日：2017-11-30

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Tymon Barwicz ,  Yves Martin ,  Jae-Woong Nah

    IPC: G02B6/13 ,  G02B6/42

    CPC classification number: G02B6/13 ,  G02B6/423 ,  G02B6/4232 ,  G02B6/4238 ,  G02B6/4249

    Abstract: A method for assembling a semiconductor device includes: receiving a first chip including a plurality of first bonding pads, a first standoff and a second standoff, wherein a first solder is deposited on each of the first bonding pads; depositing a second solder on each of the first and second standoffs; arranging a second chip over the first chip, wherein the second chip includes a plurality of second bonding pads, and at least one of the second bonding pads has a corresponding first bonding pad; heating the second chip over a melting point of the second solder to melt the second solder, and placing the second chip on the first chip to touch and solidify the second solder on each of the first and second standoffs; performing a reflow process to melt the first solder on each of the first bonding pads so that at least one of the first solders touches a corresponding second bonding pad; and waiting a predetermined period of time to allow the second chip to move until a side edge of the second chip touches a waveguide of the first chip.

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