公开(公告)号：US07795126B2

公开(公告)日：2010-09-14

申请号：US11969756

申请日：2008-01-04

申请人： Ashok Prabhu ,  Sadanand R. Patil ,  Shaw Wei Lee ,  Alexander H. Owens

发明人： Ashok Prabhu ,  Sadanand R. Patil ,  Shaw Wei Lee ,  Alexander H. Owens

IPC分类号： H01L21/00 ,  H01L21/44

CPC分类号： H01L27/14618 ,  H01L23/482 ,  H01L23/4827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device of the invention includes an integrated circuit formed on a semiconductor substrate having first and second surfaces and a notch region along the edges. The first surface includes electrical contact pads electrically connected with the integrated circuit. The first surface of the semiconductor substrate includes a top protective layer that has a surface portion extending beyond the edges of the semiconductor substrate. The second surface of the semiconductor substrate includes a bottom protective layer with electrical connectors. The surface portion of the top protective layer includes electrical contact pads that are electrically interconnected with electrical contact pad extensions. The electrical contact pad extensions are interconnected with electrical connectors via a backside electrical connector that overlaps the electrical contact pad extensions forming a lap connection. Methods for constructing such devices and connections are also disclosed.

摘要翻译： 本发明的半导体器件包括形成在具有第一和第二表面的半导体衬底上的集成电路和沿着边缘的切口区域。 第一表面包括与集成电路电连接的电接触垫。 半导体衬底的第一表面包括具有延伸超过半导体衬底的边缘的表面部分的顶部保护层。 半导体衬底的第二表面包括具有电连接器的底部保护层。 顶部保护层的表面部分包括与电接触焊盘延伸部电互连的电接触焊盘。 电接触焊盘延伸部经由背面电连接器与电连接器互连，后侧电连接器与形成搭接连接的电接触垫延伸部重叠。 还公开了用于构造这种装置和连接的方法。

公开(公告)号：US07340181B1

公开(公告)日：2008-03-04

申请号：US10145295

申请日：2002-05-13

申请人： Ashok Prabhu ,  Sadanand R. Patil ,  Shaw Wei Lee ,  Alexander H. Owens

发明人： Ashok Prabhu ,  Sadanand R. Patil ,  Shaw Wei Lee ,  Alexander H. Owens

IPC分类号： H04B10/00

CPC分类号： H01L27/14618 ,  H01L23/482 ,  H01L23/4827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device of the invention includes an integrated circuit formed on a semiconductor substrate having first and second surfaces and a notch region along the edges. The first surface includes electrical contact pads electrically connected with the integrated circuit. The first surface of the semiconductor substrate includes a top protective layer that has a surface portion extending beyond the edges of the semiconductor substrate. The second surface of the semiconductor substrate includes a bottom protective layer with electrical connectors. The surface portion of the top protective layer includes electrical contact pads that are electrically interconnected with electrical contact pad extensions. The electrical contact pad extensions are interconnected with electrical connectors via a backside electrical connector that overlaps the electrical contact pad extensions forming a lap connection. Methods for constructing such devices and connections are also disclosed.

摘要翻译： 本发明的半导体器件包括形成在具有第一和第二表面的半导体衬底上的集成电路和沿着边缘的切口区域。 第一表面包括与集成电路电连接的电接触垫。 半导体衬底的第一表面包括具有延伸超过半导体衬底的边缘的表面部分的顶部保护层。 半导体衬底的第二表面包括具有电连接器的底部保护层。 顶部保护层的表面部分包括与电接触焊盘延伸部电互连的电接触焊盘。 电接触焊盘延伸部经由背面电连接器与电连接器互连，后侧电连接器与形成搭接连接的电接触垫延伸部重叠。 还公开了用于构造这种装置和连接的方法。

公开(公告)号：US07205095B1

公开(公告)日：2007-04-17

申请号：US10666921

申请日：2003-09-17

申请人： Ashok Prabhu ,  Shaw Wei Lee

发明人： Ashok Prabhu ,  Shaw Wei Lee

IPC分类号： G03C5/00 ,  H01L31/0203

CPC分类号： H01L31/0203 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2924/0002 ,  H01L2924/00

摘要： An method and apparatus for fabricating a die having imaging circuitry and fabricating a lid having a transparent region and support regions having a predetermined height. The lid is fabricated by applying a photo-sensitive adhesive layer with a thickness substantially equal to the predetermined height to a transparent plate and patterning the photo-sensitive adhesive layer to form the transparent region and the support regions. Once fabrication of the lid is complete, it is mounted directly onto the die so that the transparent region generally covers the imaging circuitry. The resulting apparatus includes a lid mounted directly onto the die with the transparent region generally positioned above the imaging circuitry. A gap, having a height dimension substantially equal to the predetermined height of the support regions of the lid, is spaced between the transparent region of the lid and the imaging circuitry on the die.

摘要翻译： 一种用于制造具有成像电路并具有透明区域的盖子和具有预定高度的支撑区域的模具的方法和装置。 通过将具有基本上等于预定高度的厚度的光敏粘合剂层施加到透明板并图案化光敏粘合剂层以形成透明区域和支撑区域来制造盖。 一旦盖的制造完成，就将其直接安装在模具上，使得透明区域通常覆盖成像电路。 所得到的装置包括直接安装在模具上的盖，透明区域通常位于成像电路的上方。 具有基本上等于盖的支撑区域的预定高度的高度尺寸的间隙在盖的透明区域和模具上的成像电路之间间隔开。

公开(公告)号：US06873024B1

公开(公告)日：2005-03-29

申请号：US10217341

申请日：2002-08-09

申请人： Ashok Prabhu ,  Shaw Wei Lee

发明人： Ashok Prabhu ,  Shaw Wei Lee

IPC分类号： H01L31/0203 ,  H01L31/0232 ,  H01L23/02 ,  H01L23/24

CPC分类号： H01L31/0203 ,  H01L27/14618 ,  H01L27/14625 ,  H01L2224/48465 ,  H01L2224/48091 ,  H01L2924/00014

摘要： An apparatus and method for wafer level packaging of optical imaging die using conventional semiconductor packaging techniques. The method comprises forming spacing structures over imaging circuitry on a plurality of dice on a semiconductor wafer, attaching a transparent template on the spacing structures on the plurality dice on the semiconductor wafer, singulating the plurality of dice on the semiconductor wafer, and packaging the plurality of dice after being singulated from the wafer. The apparatus comprises a semiconductor wafer including a plurality of dice, each of the dice including imaging circuitry and bond pads. A translucent template is positioned over the semiconductor wafer. The translucent plate includes die cover regions configured to cover the imaging circuitry of the dice and recess regions to exposed the bond pads of the dice respectively. The resulting chip, after further packaging steps, includes the substrate, the semiconductor die having imaging circuitry and bond pads, the semiconductor die mounted onto the substrate and the transparent template positioned over the semiconductor die. The transparent template includes the a die cover region configured to be positioned over the imaging circuitry of the semiconductor die and recess regions to expose the bond pads of the semiconductor die.

摘要翻译： 一种用于使用常规半导体封装技术的光学成像芯片的晶片级封装的装置和方法。 该方法包括在半导体晶片上的多个骰子上的成像电路上形成间隔结构，在半导体晶片上的多个骰子上的间隔结构上附加透明模板，在半导体晶片上分离多个骰子，并将多个骰子 在从晶片分离后的骰子。 该装置包括包括多个骰子的半导体晶片，每个骰子包括成像电路和接合焊盘。 半透明模板位于半导体晶片上方。 半透明板包括被配置为覆盖骰子和凹陷区域的成像电路的裸片盖区域，以分别露出骰子的接合焊盘。 所得到的芯片在进一步的封装步骤之后包括衬底，具有成像电路和接合焊盘的半导体管芯，安装在衬底上的半导体管芯和位于半导体管芯上方的透明模板。 透明模板包括被配置为定位在半导体管芯的成像电路上方的裸片盖区域和凹部区域以露出半导体管芯的接合焊盘。

公开(公告)号：US06238949B1

公开(公告)日：2001-05-29

申请号：US09336037

申请日：1999-06-18

申请人： Luu Nguyen ,  Ashok Prabhu ,  Nikhil Kelkar ,  Hem P. Takiar

发明人： Luu Nguyen ,  Ashok Prabhu ,  Nikhil Kelkar ,  Hem P. Takiar

IPC分类号： H01L2144

CPC分类号： H01L24/17 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49575 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2224/92127 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method and an apparatus for forming a plastic chip on chip module is disclosed. The plastic chip on chip module is formed by placing a stacked chip set into a molding chamber suitably arranged to receive encapsulant. The stacked chip set includes a daughter chip that is electrically and mechanically coupled to a mother chip where the daughter chip is directly aligned to and separated from the mother chip by a standoff gap. Encapsulant is then passed into the molding chamber filling the standoff gap substantially simultaneously with surrounding the chip set to form the plastic chip on chip module.

摘要翻译： 公开了一种用于形成芯片上的塑料芯片模块的方法和装置。 通过将堆叠的芯片组放置在适当地布置成接收密封剂的模制室中来形成芯片上的塑料芯片模块。 堆叠的芯片组包括电子和机械耦合到母芯片的子芯片，其中子芯片通过间隙与母芯片直接对准并与母芯片分离。 然后将封装剂填充到填充间隙的模制室中，同时围绕芯片组以形成芯片上的塑料芯片模块。

公开(公告)号：US07491625B2

公开(公告)日：2009-02-17

申请号：US11691431

申请日：2007-03-26

申请人： Jaime A. Bayan ,  Nghia Tu ,  Anindya Poddar ,  Ashok Prabhu

发明人： Jaime A. Bayan ,  Nghia Tu ,  Anindya Poddar ,  Ashok Prabhu

IPC分类号： H01L21/00

CPC分类号： H01L21/6835 ,  H01L21/6836 ,  H01L24/81 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2224/16 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method of handling an IC wafer that includes a multiplicity of dice is described. Solder bumps are formed on bond pads on the active surface of the wafer. The back surface of the bumped wafer is adhered to a first mount tape. The wafer is singulated while it is still secured to the first tape to provide a multiplicity of individual dice. The active surfaces of the singulated dice are then adhered to a second tape with the first tape still adhered to the back surfaces of the dice. The first tape may then be removed. In this manner, the back surfaces of the dice may be left exposed and facing upwards with the active surfaces of the dice adhered to the second tape. The described method permits the use of a conventional die attach machine that is not designated for use as a flip-chip die attach machine.

摘要翻译： 描述了处理包括多个骰子的IC晶片的方法。 焊料凸起形成在晶片的有源表面上的接合焊盘上。 凸起的晶片的背面粘附到第一安装带。 在晶片仍被固定到第一磁带的同时将晶片单片化以提供多个独立的骰子。 然后将分割的骰子的活性表面粘附到第二带上，其中第一带仍然粘附到骰子的后表面。 然后可以移除第一个磁带。 以这种方式，骰子的后表面可以被暴露并且面向上并且骰子的活动表面粘附到第二带上。 所描述的方法允许使用未被指定用作倒装芯片连接机的常规的芯片连接机。

公开(公告)号：US06791072B1

公开(公告)日：2004-09-14

申请号：US10153974

申请日：2002-05-22

申请人： Ashok Prabhu

发明人： Ashok Prabhu

IPC分类号： H01L310203

CPC分类号： H01L27/14625 ,  H01L27/14601 ,  H01L27/14618 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/3511 ,  H05K1/0284 ,  H05K3/32 ,  H05K2201/10121 ,  H01L2924/00014

摘要： An image sensor module includes a flexible support mounted with a flexible substrate that includes optical circuitry on its surface. The substrate is formed sufficiently thin so that it can be shaped into a curved configuration. The combination of substrate and support can be mounted inside an optically transmissive housing and shaped into a variety of curved configurations that match the curved focal surface of a lens. In another approach, the support is a rigid support having a curved surface contour that substantially corresponds to a curved focal surface of a lens. The substrate is coupled with the curved surface contour of the rigid support and mounted with a lens such that the optical circuitry of the substrate obtains a curve that substantially matches that of the focal surface of the lens. Methodologies for fabricating the above modules are also disclosed.

摘要翻译： 图像传感器模块包括安装有柔性基板的柔性支撑件，该柔性基板在其表面上包括光学电路。 基底形成得足够薄，使得其可以成形为弯曲构型。 基板和支撑件的组合可以安装在透光外壳的内部并且成形为与透镜的弯曲焦点表面匹配的各种弯曲构造。 在另一种方法中，支撑件是具有基本对应于透镜的弯曲焦点表面的曲面轮廓的刚性支撑件。 衬底与刚性支撑件的弯曲表面轮廓耦合并且安装有透镜，使得衬底的光学电路获得基本上与透镜焦点表面相匹配的曲线。 还公开了用于制造上述模块的方法。

公开(公告)号：US07067354B2

公开(公告)日：2006-06-27

申请号：US10871337

申请日：2004-06-18

申请人： Ashok Prabhu

发明人： Ashok Prabhu

IPC分类号： H01L21/44

CPC分类号： H01L27/14618 ,  H01L23/482 ,  H01L23/4827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device of the invention includes an integrated circuit formed on a semiconductor substrate having first and second surfaces and edges. The first surface includes electrical contact pads electrically connected with the integrated circuit. The first surface of the semiconductor substrate includes a top protective layer that has a surface portion extending beyond the edges of the semiconductor substrate. The surface portion of the top protective layer includes electrical contact pads that are electrically connected with electrical contact pad extensions and with the integrated circuit. The second surface of the semiconductor substrate includes a multiplicity of backside electrical connectors that are in overlapping electrical contact with corresponding electrical contact pad extensions forming lap joint electrical connections between the backside electrical connectors and the corresponding electrical contact pad extensions. Methods for constructing such devices and connections are also disclosed.

公开(公告)号：US06781244B2

公开(公告)日：2004-08-24

申请号：US10310724

申请日：2002-12-04

申请人： Ashok Prabhu

发明人： Ashok Prabhu

IPC分类号： H01L2348

CPC分类号： H01L27/14618 ,  H01L23/482 ,  H01L23/4827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device of the invention includes an integrated circuit formed on a semiconductor substrate having first and second surfaces and edges. The first surface includes electrical contact pads electrically connected with the integrated circuit. The first surface of the semiconductor substrate includes a top protective layer that has a surface portion extending beyond the edges of the semiconductor substrate. The surface portion of the top protective layer includes electrical contact pads that are electrically connected with electrical contact pad extensions and with the integrated circuit. The second surface of the semiconductor substrate includes a multiplicity of backside electrical connectors that are in overlapping electrical contact with corresponding electrical contact pad extensions forming lap joint electrical connections between the backside electrical connectors and the corresponding electrical contact pad extensions. Methods for constructing such devices and connections are also disclosed.

摘要翻译： 本发明的半导体器件包括形成在具有第一和第二表面和边缘的半导体衬底上的集成电路。 第一表面包括与集成电路电连接的电接触垫。 半导体衬底的第一表面包括具有延伸超过半导体衬底的边缘的表面部分的顶部保护层。 顶部保护层的表面部分包括与电接触焊盘延伸部和集成电路电连接的电接触焊盘。 半导体衬底的第二表面包括多个背面电连接器，其与相应的电接触焊盘延伸部重叠电接触，形成背面电连接器与相应的电接触焊盘延伸部之间的搭接部电连接。 还公开了用于构造这种装置和连接的方法。

公开(公告)号：US07615407B1

公开(公告)日：2009-11-10

申请号：US12166938

申请日：2008-07-02

申请人： Anindya Poddar ,  Ashok Prabhu

发明人： Anindya Poddar ,  Ashok Prabhu

IPC分类号： H01L21/00

CPC分类号： H01L23/49589 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/28 ,  H01L24/31 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/11901 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/274 ,  H01L2224/29116 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method is described for packaging integrated circuit dice such that each package includes a die with an integrated passive component mounted to the active surface of the die.

摘要翻译： 描述了一种用于封装集成电路裸片的方法，使得每个封装包括具有安装到管芯的有源表面的集成的无源部件的管芯。