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    High-temperature bias anneal of integrated circuits for improved radiation hardness and hot electron resistance
    2.
    发明授权
    High-temperature bias anneal of integrated circuits for improved radiation hardness and hot electron resistance 失效
    集成电路的高温偏压退火，可提高辐射硬度和热电阻

    公开(公告)号：US5516731A

    公开(公告)日：1996-05-14

    申请号：US252723

    申请日：1994-06-02

    申请人： Shahin Toutounchi ,  Abraham Yee ,  Alexander H. Owens ,  Michael Lyu

    发明人： Shahin Toutounchi ,  Abraham Yee ,  Alexander H. Owens ,  Michael Lyu

    IPC分类号： H01L21/324 ,  H01L21/326 ,  H01L21/8238 ,  H01L21/477

    CPC分类号： H01L21/326 ,  H01L21/324 ,  H01L21/8238 ,  Y10S438/953

    摘要： A technique for improving the radiation hardness and hot-electron resistance of a CMOS integrated circuit is described whereby undesirable hydrogen ions may be vented through any holes, such as contact holes, in an overlying passivation layer by applying an elevated temperature and/or electrical bias to the integrated circuit die. The elevated temperature and electrical bias serve to accelerate the process by which hydrogen vents from the die. The elimination of unwanted hydrogen significantly reduces threshold shifts in the CMOS integrated circuit, providing greater radiation hardness and hot-electron resistance.

    摘要翻译： 描述了一种用于提高CMOS集成电路的辐射硬度和热电子电阻的技术，其中不期望的氢离子可以通过施加升高的温度和/或电偏压而在覆盖的钝化层中通过任何孔（例如接触孔）排出 到集成电路管芯。 升高的温度和电气偏压有助于加速从模具排出氢气的过程。 消除不需要的氢显着降低了CMOS集成电路中的阈值偏移，提供更大的辐射硬度和热电阻。

    Method of forming an MOS-type integrated circuit structure with a diode formed in the substrate under a polysilicon gate electrode to conserve space
    4.
    发明授权
    Method of forming an MOS-type integrated circuit structure with a diode formed in the substrate under a polysilicon gate electrode to conserve space 失效
    在多晶硅栅电极下方形成具有二极管的MOS型集成电路结构的方法，以节省空间

    公开(公告)号：US5661069A

    公开(公告)日：1997-08-26

    申请号：US475028

    申请日：1995-06-06

    申请人： Alexander H. Owens ,  Shahin Toutounchi

    发明人： Alexander H. Owens ,  Shahin Toutounchi

    IPC分类号： H01L27/02 ,  H01L21/70

    CPC分类号： H01L27/0255

    摘要： An improved MOS-type integrated circuit structure, and a method of making same, are described wherein a diode is electrically connected between the polysilicon gate electrode and the semiconductor substrate, and physically located in the substrate below the contact area of the polysilicon gate electrode so that no extra lateral space is needed to provide such a diode connection between the polysilicon gate electrode and the substrate. The junction is formed in the substrate in a region where the contact area of the gate electrode is usually positioned over field oxide. An opening is provided for the diode in the field oxide region of the substrate, by masking off an additional portion of the substrate, when the field oxide is initially grown, to provide for location of the diode therein.

    摘要翻译： 描述了改进的MOS型集成电路结构及其制造方法，其中二极管电连接在多晶硅栅电极和半导体衬底之间，物理地位于多晶硅栅电极的接触区域下方的衬底中，因此 在多晶硅栅电极和衬底之间不需要额外的横向空间来提供这种二极管连接。 在栅电极的接触面通常位于场氧化物上的区域中，在基板中形成结。 当场氧化物最初生长时，通过掩蔽衬底的附加部分来提供二极管在衬底的场氧化物区域中的开口，以提供二极管的位置。

    Testing an embedded core
    5.
    发明授权
    Testing an embedded core 有权
    测试嵌入式核心

    公开(公告)号：US07917820B1

    公开(公告)日：2011-03-29

    申请号：US12123867

    申请日：2008-05-20

    申请人： Adarsh Pavle ,  Shahin Toutounchi

    发明人： Adarsh Pavle ,  Shahin Toutounchi

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318597 ,  G11C29/32 ,  G11C2029/0401 ,  G11C2029/3202

    摘要： A method of testing of an embedded core of an integrated circuit (“IC”) is described. An IC has a hardwired embedded core and memory coupled to each other in the IC. The method includes writing a test vector to the memory while the embedded core is operative. The test vector is input from the memory to the embedded core to mimic scan chain input to the embedded core. A test result is obtained from the embedded core responsive in part to the test vector input.

    摘要翻译： 描述了集成电路（“IC”）的嵌入式核心的测试方法。 IC具有在IC中彼此耦合的硬连线的嵌入式核心和存储器。 该方法包括在嵌入式核心工作时将测试向量写入存储器。 测试向量从存储器输入到嵌入式核心，以模拟到嵌入式核心的扫描链输入。 测试结果从嵌入式核心获得部分响应于测试矢量输入。

    Automated fault diagnosis in a programmable device
    6.
    发明授权
    Automated fault diagnosis in a programmable device 有权
    可编程器件中的自动故障诊断

    公开(公告)号：US07219287B1

    公开(公告)日：2007-05-15

    申请号：US10955560

    申请日：2004-09-29

    申请人： Shahin Toutounchi ,  Andrew M. Taylor

    发明人： Shahin Toutounchi ,  Andrew M. Taylor

    IPC分类号： G01R31/28 ,  G06F11/00 ,  G06F19/00 ,  G06F15/00

    CPC分类号： G01R31/31835 ,  G01R31/318516 ,  Y10S707/99953

    摘要： A method and apparatus are disclosed that simplify and reduce the time required for detecting faults in a programmable device such as a programmable logic device (PLD) by utilizing fault coverage information corresponding to a plurality of test patterns for the PLD to reduce the set of potential faults. For one embodiment, each test pattern is designated as either passing or failing, the faults that are detectable by at least two failing test patterns and the faults that are not detectable by any passing test patterns are eliminated, and the remaining faults are diagnosed. For another embodiment, the faults detectable by each failing test pattern are diagnosed to generate corresponding fault sets, and the faults not common to the fault sets and not detectable by one or more of the failing test patterns are eliminated.

    摘要翻译： 公开了一种方法和装置，其通过利用与PLD的多个测试模式对应的故障覆盖信息来简化和减少检测诸如可编程逻辑器件（PLD）的可编程设备中的故障所需的时间，以减少潜在的电位 故障 对于一个实施例，将每个测试模式指定为通过或失败，可以消除由至少两个故障测试模式可检测的故障，并且消除由任何通过的测试模式无法检测到的故障，并且诊断剩余的故障。 对于另一个实施例，可以诊断每个故障测试模式可检测到的故障以产生相应的故障集，并且消除由一个或多个故障测试模式不能检测到的故障集合不常见的故障。

    Method for testing faults in a programmable logic device
    7.
    发明授权
    Method for testing faults in a programmable logic device 有权
    用于测试可编程逻辑器件中的故障的方法

    公开(公告)号：US06732309B1

    公开(公告)日：2004-05-04

    申请号：US09921115

    申请日：2001-08-02

    申请人： Shahin Toutounchi ,  Andrew W. Lai

    发明人： Shahin Toutounchi ,  Andrew W. Lai

    IPC分类号： G01R3128

    CPC分类号： G01R31/318516

    摘要： A new method to test short faults in a programmable logic device is described. The line segments under test are connected together to form a conducting chain. All the line segments neighboring to the conducting chain are tied to a known state. A test vector is applied to the programmable logic device. The state of the line under test is measured. If it is the same as the known state, the programmable logic device is likely to have faults.

    摘要翻译： 描述了一种在可编程逻辑器件中测试短路故障的新方法。 被测线路连接在一起形成导电链。 与导向链相邻的所有线段被绑定到已知状态。 将测试矢量应用于可编程逻辑器件。 测量被测线路的状态。 如果与已知状态相同，则可编程逻辑器件可能存在故障。

    PMOS three-terminal non-volatile memory element and method of programming
    9.
    发明授权
    PMOS three-terminal non-volatile memory element and method of programming 有权
    PMOS三端非易失性存储元件及编程方法

    公开(公告)号：US07450431B1

    公开(公告)日：2008-11-11

    申请号：US11210496

    申请日：2005-08-24

    申请人： James Karp ,  Jongheon Jeong ,  Michael G. Ahrens ,  Shahin Toutounchi

    发明人： James Karp ,  Jongheon Jeong ,  Michael G. Ahrens ,  Shahin Toutounchi

    IPC分类号： G11C16/04

    CPC分类号： G11C17/16

    摘要： A PMOS transistor is programmed as a non-volatile memory element by operating the PMOS transistor in accumulation mode. This facilitates merging the source and drain regions to form a low-resistance path because most heating occurs on the channel side of the gate dielectric, rather than on the gate terminal side. In a particular embodiment, boron is used as the dopant. Boron has a higher diffusivity than arsenic or phosphorous, which are typical n-type dopants. Boron's higher diffusivity promotes merging the source and drain regions.

    摘要翻译： 通过在累积模式下操作PMOS晶体管，将PMOS晶体管编程为非易失性存储元件。 这有助于将源极和漏极区域合并以形成低电阻路径，因为大多数加热发生在栅极电介质的沟道侧，而不是栅极端子侧。 在一个具体实施方案中，使用硼作为掺杂剂。 硼具有比砷或磷更高的扩散性，它们是典型的n型掺杂剂。 硼的较高扩散性促进了源区和漏区的融合。

    Built-in self test (BIST) technology for testing field programmable gate arrays (FPGAs) using partial reconfiguration
    10.
    发明授权
    Built-in self test (BIST) technology for testing field programmable gate arrays (FPGAs) using partial reconfiguration 有权
    内置自检（BIST）技术，用于使用部分重配置测试现场可编程门阵列（FPGA）

    公开(公告)号：US07302625B1

    公开(公告)日：2007-11-27

    申请号：US11284455

    申请日：2005-11-21

    申请人： Tassanee Payakapan ,  Lee Ni Chung ,  Shahin Toutounchi

    发明人： Tassanee Payakapan ,  Lee Ni Chung ,  Shahin Toutounchi

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318519 ,  G01R31/3187 ,  G06F17/5054 ,  G06F2217/14

    摘要： A Built-in Self Test (BIST) system is provided in a Field Programmable Gate Array (FPGA) that can adjust test signal patterns provided for testing after partial reconfiguration of the FPGA. The BIST system includes a decoder that monitors I/O signals and provides an output indicating when I/O signals change indicating partial reconfiguration has occurred. The decoder output is provided to a BIST test signal generator providing signals to an IP core of the FPGA as well as a BIST comparator for monitoring test results to change test signals depending on the partial configuration mode.

    摘要翻译： 在现场可编程门阵列（FPGA）中提供了内置自测（BIST）系统，该阵列可以调整FPGA部分重新配置后提供的测试信号模式。 BIST系统包括一个监视I / O信号的解码器，并提供一个输出，指示何时I / O信号变化，表明发生了部分重新配置。 解码器输出提供给BIST测试信号发生器，向FPGA的IP内核提供信号，以及BIST比较器，用于监视测试结果，以根据部分配置模式更改测试信号。