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公开(公告)号：US20160141463A1
公开(公告)日：2016-05-19
申请号：US15004478
申请日：2016-01-22
Applicant: Juanita Kurtin , Brian Theobald , Matthew J. Carillo , Oun-Ho Park , Georgeta Masson , Steven M. Hughes
Inventor： Juanita Kurtin , Brian Theobald , Matthew J. Carillo , Oun-Ho Park , Georgeta Masson , Steven M. Hughes
IPC: H01L33/50
CPC classification number: H01L33/502 , B82Y20/00 , B82Y30/00 , B82Y40/00 , C01B19/007 , C01P2002/84 , C01P2004/04 , C01P2004/10 , C01P2004/54 , C01P2004/64 , C01P2004/80 , C09K11/02 , C09K11/025 , C09K11/565 , C09K11/883 , H01L33/005 , H01L33/06 , H01L33/56 , H01L2933/0033 , H01L2933/0041 , H01L2933/005 , H01L2933/0083 , Y10S977/744 , Y10S977/774 , Y10S977/824 , Y10S977/89 , Y10S977/95
Abstract: Semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell and insulator coating, wherein the semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material, and an anisotropic nanocrystalline shell composed of a second, different, semiconductor material surrounding the anisotropic nanocrystalline core. The anisotropic nanocrystalline core and the anisotropic nanocrystalline shell form a quantum dot. An insulator layer encapsulates the nanocrystalline shell and anisotropic nanocrystalline core.
Abstract translation: 具有纳米晶核和对应的纳米晶体壳和绝缘体涂层的半导体结构，其中所述半导体结构包括由第一半导体材料构成的各向异性纳米晶核和由围绕所述各向异性纳米晶核的第二不同半导体材料组成的各向异性纳米晶体壳。 各向异性纳米晶核和各向异性纳米晶体壳形成量子点。 绝缘体层封装纳米晶体壳和各向异性纳米晶核。
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公开(公告)号：US08513741B2
公开(公告)日：2013-08-20
申请号：US13216120
申请日：2011-08-23
Applicant: Ali Keshavarzi , Juanita Kurtin , Vivek De
Inventor： Ali Keshavarzi , Juanita Kurtin , Vivek De
IPC: H01L51/05
CPC classification number: H03K19/20 , B82Y10/00 , H01L27/283 , H01L51/0048 , H01L51/0541 , Y10S977/742 , Y10S977/938
Abstract: In accordance with some embodiments, logical circuits comprising carbon nanotube field effect transistors are disclosed herein.
Abstract translation: 根据一些实施例，本文公开了包括碳纳米管场效应晶体管的逻辑电路。
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3.发明申请SEMICONDUCTOR STRUCTURE HAVING NANOCRYSTALLINE CORE AND NANOCRYSTALLINE SHELL WITH INSULATOR COATING 审中-公开具有纳米晶核和具有绝缘体涂层的纳米晶体壳的半导体结构公开(公告)号：US20130112941A1
公开(公告)日：2013-05-09
申请号：US13485761
申请日：2012-05-31
Applicant: Juanita Kurtin , Matthew J. Carillo , Steven Hughes , Brian Theobald , Colin Reese , Oun-Ho Park , Georgeta Masson
Inventor： Juanita Kurtin , Matthew J. Carillo , Steven Hughes , Brian Theobald , Colin Reese , Oun-Ho Park , Georgeta Masson
IPC: H01L33/06
CPC classification number: H01L33/06 , B01J13/02 , B82Y30/00 , B82Y40/00 , B82Y99/00 , C01B19/007 , C01P2002/84 , C01P2004/04 , C01P2004/10 , C01P2004/54 , C01P2004/64 , C01P2004/80 , C09K11/02 , C09K11/025 , C09K11/565 , C09K11/883 , H01L21/02422 , H01L21/02557 , H01L21/0256 , H01L21/02601 , H01L21/02628 , H01L33/002 , H01L33/005 , H01L33/04 , H01L33/502
Abstract: Semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell and insulator coating are described. In an example, a semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material and having an aspect ratio between, but not including, 1.0 and 2.0. The semiconductor structure also includes a nanocrystalline shell composed of a second, different, semiconductor material at least partially surrounding the anisotropic nanocrystalline core. An insulator layer encapsulates the nanocrystalline shell and anisotropic nanocrystalline core.
Abstract translation: 描述了具有纳米晶核和对应的纳米晶体壳和绝缘体涂层的半导体结构。 在一个示例中，半导体结构包括由第一半导体材料构成并且具有但不包括1.0和2.0之间的纵横比的各向异性纳米晶核。 半导体结构还包括由至少部分地围绕各向异性纳米晶核的第二不同的半导体材料组成的纳米晶体壳。 绝缘体层封装纳米晶体壳和各向异性纳米晶核。
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公开(公告)号：US20090003028A1
公开(公告)日：2009-01-01
申请号：US11824321
申请日：2007-06-29
Applicant: Ali Keshavarzi , Juanita Kurtin , Janice C. Lee , Vivek De , Tanay Karnik , Timothy L. Deeter
Inventor： Ali Keshavarzi , Juanita Kurtin , Janice C. Lee , Vivek De , Tanay Karnik , Timothy L. Deeter
CPC classification number: G11C17/16 , B82Y10/00 , G11C13/025 , G11C17/165 , G11C2213/17 , H01L23/5256 , H01L27/101 , H01L2924/0002 , H01L2924/00
Abstract: In one embodiment of the invention, a fuse element for a one time programmable memory may include carbon nanotubes coupled to a first transistor node and to a second transistor node. The carbon nanotubes may have a first resistance which may be changed upon programming the memory cell with low current levels.
Abstract translation: 在本发明的一个实施例中，用于一次可编程存储器的熔丝元件可以包括耦合到第一晶体管节点和第二晶体管节点的碳纳米管。 碳纳米管可以具有在以低电流水平编程存储器单元时可以改变的第一电阻。
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5.发明授权Methods of forming carbon nanotube transistors for high speed circuit operation and structures formed thereby 失效形成用于高速电路操作的碳纳米管晶体管的方法和由此形成的结构公开(公告)号：US08389976B2
公开(公告)日：2013-03-05
申请号：US11648209
申请日：2006-12-29
Applicant: Arijit Raychowdhury , Ali Keshavarzi , Juanita Kurtin , Vivek De
Inventor： Arijit Raychowdhury , Ali Keshavarzi , Juanita Kurtin , Vivek De
IPC: H01L29/06
CPC classification number: H01L29/0665 , B82Y10/00 , H01L27/283 , H01L29/0673 , H01L51/0048 , H01L51/0541 , H01L51/055 , H01L51/0558
Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming a channel region on a substrate, wherein the channel region comprises at least one CNT, forming at least one source/drain region adjacent the channel region, and then forming a gate electrode on the channel region, wherein a width of the gate electrode comprises about 50 percent to about 90 percent of a width of the contact region.
Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括在衬底上形成沟道区，其中沟道区包括至少一个CNT，形成与沟道区相邻的至少一个源/漏区，然后在沟道区上形成栅电极，其中宽度 栅电极占接触区域宽度的约50％至约90％。
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Patent Agency Ranking
公开(公告)号：US07787292B2
公开(公告)日：2010-08-31
申请号：US11824321
申请日：2007-06-29
Applicant: Ali Keshavarzi , Juanita Kurtin , Janice C. Lee , Vivek De , Tanay Karnik , Timothy L. Deeter
Inventor： Ali Keshavarzi , Juanita Kurtin , Janice C. Lee , Vivek De , Tanay Karnik , Timothy L. Deeter
IPC: G11C11/34
CPC classification number: G11C17/16 , B82Y10/00 , G11C13/025 , G11C17/165 , G11C2213/17 , H01L23/5256 , H01L27/101 , H01L2924/0002 , H01L2924/00
Abstract: In one embodiment of the invention, a fuse element for a one time programmable memory may include carbon nanotubes coupled to a first transistor node and to a second transistor node. The carbon nanotubes may have a first resistance which may be changed upon programming the memory cell with low current levels.
Abstract translation: 在本发明的一个实施例中，用于一次可编程存储器的熔丝元件可以包括耦合到第一晶体管节点和第二晶体管节点的碳纳米管。 碳纳米管可以具有在以低电流水平编程存储器单元时可以改变的第一电阻。
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公开(公告)号：US20130112942A1
公开(公告)日：2013-05-09
申请号：US13485762
申请日：2012-05-31
Applicant: Juanita Kurtin , Matthew J. Carillo , Steven M. Hughes , Brian Theobald , Colin Reese , Oun-Ho Park , Georgeta Masson
Inventor： Juanita Kurtin , Matthew J. Carillo , Steven M. Hughes , Brian Theobald , Colin Reese , Oun-Ho Park , Georgeta Masson
IPC: H01L33/06
CPC classification number: H01L33/502 , B82Y20/00 , B82Y30/00 , B82Y40/00 , C01B19/007 , C01P2002/84 , C01P2004/04 , C01P2004/10 , C01P2004/54 , C01P2004/64 , C01P2004/80 , C09K11/02 , C09K11/025 , C09K11/565 , C09K11/883 , H01L33/005 , H01L33/06 , H01L33/56 , H01L2933/0033 , H01L2933/0041 , H01L2933/005 , H01L2933/0083 , H05K999/99 , Y10S977/744 , Y10S977/774 , Y10S977/824 , Y10S977/89 , Y10S977/95
Abstract: Composites having semiconductor structures embedded in a matrix are described. In an example, a composite includes a matrix material. A plurality of semiconductor structures is embedded in the matrix material. Each semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material and having an aspect ratio between, but not including, 1.0 and 2.0. Each semiconductor structure also includes a nanocrystalline shell composed of a second, different, semiconductor material at least partially surrounding the anisotropic nanocrystalline core. An insulator layer encapsulates each nanocrystalline shell and anisotropic nanocrystalline core pairing.
Abstract translation: 描述了具有嵌入矩阵中的半导体结构的复合材料。 在一个实例中，复合材料包括基体材料。 多个半导体结构嵌入基体材料中。 每个半导体结构包括由第一半导体材料构成并具有但不包括1.0和2.0之间的纵横比的各向异性纳米晶核。 每个半导体结构还包括由至少部分地围绕各向异性纳米晶核的第二不同的半导体材料组成的纳米晶体壳。 绝缘体层封装每个纳米晶体壳和各向异性纳米晶核心配对。
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8.发明申请Methods of forming carbon nanotube transistors for high speed circuit operation and structures formed thereby 失效形成用于高速电路操作的碳纳米管晶体管的方法和由此形成的结构公开(公告)号：US20100252812A1
公开(公告)日：2010-10-07
申请号：US11648209
申请日：2006-12-29
Applicant: Arijit Raychowdhury , Ali Keshavarzi , Juanita Kurtin , Vivek De
Inventor： Arijit Raychowdhury , Ali Keshavarzi , Juanita Kurtin , Vivek De
CPC classification number: H01L29/0665 , B82Y10/00 , H01L27/283 , H01L29/0673 , H01L51/0048 , H01L51/0541 , H01L51/055 , H01L51/0558
Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming a channel region on a substrate, wherein the channel region comprises at least one CNT, forming at least one source/drain region adjacent the channel region, and then forming a gate electrode on the channel region, wherein a width of the gate electrode comprises about 50 percent to about 90 percent of a width of the contact region.
Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括在衬底上形成沟道区，其中沟道区包括至少一个CNT，形成与沟道区相邻的至少一个源/漏区，然后在沟道区上形成栅电极，其中宽度 栅电极占接触区域宽度的约50％至约90％。
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公开(公告)号：US20070078613A1
公开(公告)日：2007-04-05
申请号：US11241182
申请日：2005-09-30
Applicant: Juanita Kurtin
Inventor： Juanita Kurtin
IPC: G01R15/00
CPC classification number: G03F7/70391 , B82Y10/00 , G03F7/2014 , G03F7/70216 , G03F7/70383
Abstract: An embodiment of the present invention is a technique to pattern features. An array of nanowires is placed at a distance to a resist layer. The array forms a plurality of light emitting diodes (LEDs). The distance corresponds to a near-field region of the light emitted by the LEDs with respect to the resist layer. A control circuit controls the LEDs to emit the light to pattern a feature in the resist layer.
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10.发明授权公开(公告)号：US09159872B2
公开(公告)日：2015-10-13
申请号：US13485756
申请日：2012-05-31
Applicant: Juanita Kurtin , Matthew J. Carillo , Steven Hughes
Inventor： Juanita Kurtin , Matthew J. Carillo , Steven Hughes
IPC: H01L29/06 , H01L33/04 , H01L21/02 , H01L33/50 , C09K11/02 , C09K11/56 , C09K11/88 , C01B19/00 , H01L33/06 , B82Y30/00 , H01L33/00 , B01J13/02 , B82Y40/00 , B82Y99/00
CPC classification number: H01L33/06 , B01J13/02 , B82Y30/00 , B82Y40/00 , B82Y99/00 , C01B19/007 , C01P2002/84 , C01P2004/04 , C01P2004/10 , C01P2004/54 , C01P2004/64 , C01P2004/80 , C09K11/02 , C09K11/025 , C09K11/565 , C09K11/883 , H01L21/02422 , H01L21/02557 , H01L21/0256 , H01L21/02601 , H01L21/02628 , H01L33/005 , H01L33/04 , H01L33/502
Abstract: Semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell are described. In an example, a semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material and having an aspect ratio between, but not including, 1.0 and 2.0. The semiconductor structure also includes a nanocrystalline shell composed of a second, different, semiconductor material at least partially surrounding the anisotropic nanocrystalline core.
Abstract translation: 描述了具有纳米晶核和对应的纳米晶体壳的半导体结构。 在一个示例中，半导体结构包括由第一半导体材料构成并且具有但不包括1.0和2.0之间的纵横比的各向异性纳米晶核。 半导体结构还包括由至少部分地围绕各向异性纳米晶核的第二不同的半导体材料组成的纳米晶体壳。
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