利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

24 条记录 (耗时 0.021 秒)

    ASSIST CIRCUIT FOR MEMORY
    2.
    发明申请
    ASSIST CIRCUIT FOR MEMORY 有权
    记忆辅助电路

    公开(公告)号：US20150279438A1

    公开(公告)日：2015-10-01

    申请号：US14229767

    申请日：2014-03-28

    申请人： Jaydeep P. Kulkarni ,  Anupama Thaploo ,  Iqbal Rajwani ,  Kyung-Hoae Koo ,  Eric A. Karl ,  Muhammad Khellah

    发明人： Jaydeep P. Kulkarni ,  Anupama Thaploo ,  Iqbal Rajwani ,  Kyung-Hoae Koo ,  Eric A. Karl ,  Muhammad Khellah

    IPC分类号： G11C7/12 ,  G11C17/16 ,  G11C7/22

    CPC分类号： G11C7/12 ,  G11C7/1048 ,  G11C7/1069 ,  G11C7/22 ,  G11C11/419 ,  G11C17/16 ,  G11C2207/005

    摘要： Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.

    摘要翻译： 实施例包括与可以耦合到存储器系统的一个或多个部件的辅助电路相关的装置，方法和系统，以选择性地降低传送到部件的电源电压。 例如，辅助电路可以耦合到多个比特单元（例如，寄存器文件比特单元）。 辅助电路可以在写入操作的至少一部分期间和/或在位单元的非活动状态期间选择性地降低传送到位单元的电源电压。 另外或替代地，辅助电路可以耦合到读取电路，以在读取电路的非活动状态期间选择性地降低传送到读取电路的电源电压。 辅助电路可以包括与主电源轨和位单元和/或读电路的供电节点之间的一个或多个二极管并联耦合的控制晶体管。

    Multi-supply sequential logic unit
    3.
    发明授权
    Multi-supply sequential logic unit 有权
    多电源顺序逻辑单元

    公开(公告)号：US08901819B2

    公开(公告)日：2014-12-02

    申请号：US13992894

    申请日：2011-12-14

    申请人： Arijit Raychowdhury ,  Jaydeep P. Kulkarni ,  James W. Tschanz

    发明人： Arijit Raychowdhury ,  Jaydeep P. Kulkarni ,  James W. Tschanz

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/017509 ,  G06F1/10 ,  G06F1/3296 ,  Y02D10/172

    摘要： Described herein are apparatus, method, and system for reducing clock-to-output delay of a sequential logic unit in a processor. The apparatus comprises a sequential unit including: a data path, to receive an input signal, including logic gates to operate on a first power supply level, the data path to generate an output signal; and a clock path including logic gates to operate on a second power supply level, the logic gates of the clock path to sample the input signal using a sampling signal to generate the output signal, wherein the second power supply level is higher than the first power supply level. The apparatus improves (i.e. reduces) setup time of the sequential unit and allows the processor to operate at minimum operating voltage (Vmin) without degrading performance of the sequential unit.

    摘要翻译： 这里描述了用于减少处理器中的顺序逻辑单元的时钟到输出延迟的装置，方法和系统。 所述装置包括顺序单元，包括：数据路径，用于接收输入信号，包括在第一电源电平上操作的逻辑门，所述数据路径以产生输出信号; 以及时钟路径，包括用于在第二电源电平上操作的逻辑门，所述时钟路径的逻辑门使用采样信号对所述输入信号进行采样以产生所述输出信号，其中所述第二电源电平高于所述第一电力 供应水平。 该装置改善（即减少）顺序单元的建立时间，并允许处理器以最小工作电压（Vmin）运行，而不降低顺序单元的性能。

    Adaptive self-repairing cache
    4.
    发明授权
    Adaptive self-repairing cache 有权
    自适应自修复缓存

    公开(公告)号：US08719502B2

    公开(公告)日：2014-05-06

    申请号：US13436758

    申请日：2012-03-30

    申请人： Christopher B. Wilkerson ,  Alaa R. Alameldeen ,  Jaydeep P. Kulkarni

    发明人： Christopher B. Wilkerson ,  Alaa R. Alameldeen ,  Jaydeep P. Kulkarni

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0802 ,  G06F2212/1032 ,  G06F2212/604 ,  Y02D10/13

    摘要： A method for operating a cache that includes both robust cells and standard cells may include receiving a data to be written to the cache, determining whether a type of the data is unmodified data or modified data, and writing the data to robust cells or standard cells as a function of the type of the data. A processor includes a core that includes a cache including both robust cells and standard cells for receiving data, wherein the data is written to robust cells or standard cells as a function of whether a type of the data is determined to be unmodified data or modified data.

    摘要翻译： 用于操作包括鲁棒单元和标准单元的高速缓存的方法可以包括接收要写入高速缓存的数据，确定数据类型是未修改数据还是修改数据，以及将数据写入鲁棒单元或标准单元 作为数据类型的函数。 处理器包括核心，其包括包括鲁棒单元和用于接收数据的标准单元的高速缓存，其中根据是否将数据类型确定为未修改数据或修改数据，将数据写入鲁棒单元或标准单元 。

    APPARATUS FOR REDUCING WRITE MINIMUM SUPPLY VOLTAGE FOR MEMORY
    6.
    发明申请
    APPARATUS FOR REDUCING WRITE MINIMUM SUPPLY VOLTAGE FOR MEMORY 有权
    用于减少存储器的最小供电电压的装置

    公开(公告)号：US20140003132A1

    公开(公告)日：2014-01-02

    申请号：US13536521

    申请日：2012-06-28

    申请人： Jaydeep P. Kulkarni ,  Muhammad M Khellah ,  James W. Tschanz ,  Bibiche M. Geuskens ,  Vivek K. De

    发明人： Jaydeep P. Kulkarni ,  Muhammad M Khellah ,  James W. Tschanz ,  Bibiche M. Geuskens ,  Vivek K. De

    IPC分类号： G11C7/12 ,  G11C11/00 ,  G11C7/00

    CPC分类号： G11C11/419 ,  G11C7/227 ,  G11C11/412 ,  G11C11/413

    摘要： Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation.

    摘要翻译： 描述了一种用于存储元件的写入最小电源电压的自感应降低的装置。 该装置包括：具有耦合到第一电源节点的交叉耦合的反相器的存储元件; 耦合到第一电源节点和第二电源节点的电源设备，第二电源节点耦合到电源; 以及具有耦合到字线的栅极端子，耦合到存储器元件的第一端子和耦合到位线的第二端子的存取装置，该位线可操作以在写入之前预放电到逻辑低电平 操作。