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    Real time automatic and background calibration at embedded duty cycle correlation
    3.
    发明授权
    Real time automatic and background calibration at embedded duty cycle correlation 有权
    嵌入式占空比相关的实时自动和背景校准

    公开(公告)号：US09148135B2

    公开(公告)日：2015-09-29

    申请号：US13532881

    申请日：2012-06-26

    申请人： Matt Li ,  Tsung-Hsien Tsai ,  Mao-Hsuan Chou ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    发明人： Matt Li ,  Tsung-Hsien Tsai ,  Mao-Hsuan Chou ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    IPC分类号： G06F1/00 ,  H03K5/156 ,  G06F1/08

    CPC分类号： H03K5/1565 ,  G06F1/08

    摘要： The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values.

    摘要翻译： 本公开涉及一种时钟发生系统。 该系统包括时钟源，调谐缓冲器，输出缓冲器，占空比测量电路和自动校准部件。 时钟源产生时钟信号。 调谐缓冲器被配置为根据调整值从时钟信号产生校正的时钟信号。 输出缓冲器被配置为从校正的时钟信号产生输出时钟信号。 配置占空比测量电路来测量输出时钟信号的占空比。 自动校准部件被配置为根据占空比测量值和规格值生成调整值。

    PLL with oscillator PVT compensation
    4.
    发明授权
    PLL with oscillator PVT compensation 有权
    PLL振荡器PVT补偿

    公开(公告)号：US08963649B2

    公开(公告)日：2015-02-24

    申请号：US13731687

    申请日：2012-12-31

    申请人： Matt Li ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    发明人： Matt Li ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    IPC分类号： H03L1/00 ,  H03L7/06 ,  H03B5/10

    CPC分类号： H03L1/00 ,  H03B5/10 ,  H03L7/06 ,  H03L7/099 ,  H03L7/0992

    摘要： A voltage controlled oscillator (VCO) includes a current controlled oscillator, a voltage-to-current converter, and a sensing circuit. The sensing circuit includes a delay unit, and the sensing circuit is configured to generate a plurality of compensation control signals in response to a time delay of the delay unit. The voltage-to-current converter is configured to generate a current signal in response to a VCO control signal and the plurality of compensation control signals. The current controlled oscillator is configured to generate an oscillating signal in response to the current signal.

    摘要翻译： 压控振荡器（VCO）包括电流控制振荡器，电压 - 电流转换器和感测电路。 感测电路包括延迟单元，并且感测电路被配置为响应于延迟单元的时间延迟而产生多个补偿控制信号。 电压 - 电流转换器被配置为响应于VCO控制信号和多个补偿控制信号而产生电流信号。 电流控制振荡器被配置为响应于当前信号产生振荡信号。

    Real Time Automatic and Background Calibration at Embedded Duty Cycle Correlation
    5.
    发明申请
    Real Time Automatic and Background Calibration at Embedded Duty Cycle Correlation 有权
    嵌入式占空比相关的实时自动和背景校准

    公开(公告)号：US20130342252A1

    公开(公告)日：2013-12-26

    申请号：US13532881

    申请日：2012-06-26

    申请人： Matt Li ,  Tsung-Hsien Tsai ,  Mao-Hsuan Chou ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    发明人： Matt Li ,  Tsung-Hsien Tsai ,  Mao-Hsuan Chou ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    IPC分类号： H03K3/017

    CPC分类号： H03K5/1565 ,  G06F1/08

    摘要： The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values.

    摘要翻译： 本公开涉及一种时钟发生系统。 该系统包括时钟源，调谐缓冲器，输出缓冲器，占空比测量电路和自动校准部件。 时钟源产生时钟信号。 调谐缓冲器被配置为根据调整值从时钟信号产生校正的时钟信号。 输出缓冲器被配置为从校正的时钟信号产生输出时钟信号。 配置占空比测量电路来测量输出时钟信号的占空比。 自动校准部件被配置为根据占空比测量值和规格值生成调整值。

    SEMICONDUCTOR DEVICE DESIGN SYSTEM AND METHOD OF USING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE DESIGN SYSTEM AND METHOD OF USING THE SAME 有权
    半导体器件设计系统及其使用方法

    公开(公告)号：US20130311957A1

    公开(公告)日：2013-11-21

    申请号：US13475853

    申请日：2012-05-18

    申请人： Chih-Hsien CHANG ,  Yung-Chow PENG ,  Fu-Lung HSUEH

    发明人： Chih-Hsien CHANG ,  Yung-Chow PENG ,  Fu-Lung HSUEH

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G03F1/00 ,  G06F17/5009 ,  G06F17/5045 ,  G06F17/5068 ,  G06F19/00 ,  G06F2217/12 ,  G21K5/00

    摘要： A circuit design system includes a schematic design tool configured to generate schematic information and pre-coloring information for a circuit. The circuit design system also includes a netlist file configured to store the schematic information and the pre-coloring information on a non-transitory computer readable medium and an extraction tool configured to extract the pre-coloring information from the netlist file. A layout design tool, included in the circuit design system, is configured to design at least one mask based on the schematic information and the pre-coloring information. The circuit design system further includes a layout versus schematic comparison tool configured to compare the at least one mask to the schematic information and the pre-coloring information.

    摘要翻译： 电路设计系统包括被配置为产生电路的示意图信息和预着色信息的示意性设计工具。 电路设计系统还包括被配置为在非暂时计算机可读介质上存储原理图信息和预着色信息的网表文件，以及被配置为从网表文件中提取预着色信息的提取工具。 包括在电路设计系统中的布局设计工具被配置为基于原理图信息和预着色信息设计至少一个掩模。 电路设计系统还包括布局与示意性比较工具，其被配置为将至少一个掩模与示意图信息和预着色信息进行比较。

    High speed communication interface with an adaptive swing driver to reduce power consumption
    8.
    发明授权
    High speed communication interface with an adaptive swing driver to reduce power consumption 有权

    公开(公告)号：US08410818B1

    公开(公告)日：2013-04-02

    申请号：US13372978

    申请日：2012-02-14

    申请人： Ying-Yu Hsu ,  Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    发明人： Ying-Yu Hsu ,  Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    IPC分类号： H03K19/094

    CPC分类号： H03K3/012 ,  H03K19/0013 ,  H03K19/018521

    摘要： A high-speed bus interface with an adaptive swing driver. A high speed interface includes a transmitter and a receiver coupled via a bus. The transmitter has an adaptive swing driver and a voltage-regulating-module (VRM). The adaptive swing driver includes a post-driver and a pre-driver. The post-driver provides an adaptive swing output with a dedicated adaptive voltage power supply (VDDQ) and transition emphasis driving capacity with an internal logic voltage supply (VDD). The pre-driver provides the transition emphasis driving capacity with a pull-up and a pull-down signal path to the post-driver. The voltage-regulating-module is configured to supply signal to the adaptive swing driver. The receiver includes a comparator and a bit-error-rate detector. The comparator amplifies the adaptive swing output received from the transmitter via a bus, while the bit-error-rate detector diagnoses the amplified adaptive swing output received from the comparator.

    METHOD AND APPARATUS FOR SIGNAL PHASE CALIBRATION
    9.
    发明申请
    METHOD AND APPARATUS FOR SIGNAL PHASE CALIBRATION 有权
    信号相位校准的方法和装置

    公开(公告)号：US20130063181A1

    公开(公告)日：2013-03-14

    申请号：US13228508

    申请日：2011-09-09

    申请人： Mao-Hsuan CHOU ,  Min-Shueh YUAN ,  Chih-Hsien CHANG

    发明人： Mao-Hsuan CHOU ,  Min-Shueh YUAN ,  Chih-Hsien CHANG

    IPC分类号： H03D13/00

    CPC分类号： H03K5/135 ,  H03B19/00 ,  H03L7/099

    摘要： A method for signal phase calibration includes providing multiple periodic clock signals, including a reference signal and multiple phase shifted versions of the reference signal. The signals have a common frequency and are shifted from one another by multiples of a phase offset. An edge of a first signal is detected. The first signal is one of multiple phase shifted versions of the reference signal. The edge is a transition from a first logic value to a second logic value. The second logic value of the first signal is compared, upon detection of the edge, to a logic value of a second signal that is one of the first plurality of periodic clock signals other than the first signal. An inversion of the first signal is selectively provided based on an outcome of the comparison.

    摘要翻译： 用于信号相位校准的方法包括提供多个周期性时钟信号，包括参考信号和参考信号的多个相移版本。 这些信号具有共同的频率并且相互偏移倍数的相位偏移。 检测到第一信号的边缘。 第一个信号是参考信号的多个相移版本之一。 边缘是从第一逻辑值到第二逻辑值的转换。 第一信号的第二逻辑值在检测到边缘时被比较为除了第一信号之外的第一多个周期性时钟信号之一的第二信号的逻辑值。 基于比较的结果选择性地提供第一信号的反转。

    I/O CELL ARCHITECTURE
    10.
    发明申请
    I/O CELL ARCHITECTURE 有权
    I / O CELL ARCHITECTURE

    公开(公告)号：US20120124531A1

    公开(公告)日：2012-05-17

    申请号：US12947938

    申请日：2010-11-17

    申请人： Renjeng CHIANG ,  Chih-Hsien CHANG

    发明人： Renjeng CHIANG ,  Chih-Hsien CHANG

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G06F2217/40

    摘要： A system includes a computer readable storage medium and a processor. The computer readable storage includes data representing an input/output (“I/O”) cell of a first type for modeling and/or fabricating a semiconductor device. The I/O cell of the first type includes circuitry for providing a first plurality of functions. The processor is in communication with the computer readable storage medium and is configured to select the I/O cell of the first type, arrange a plurality of the I/O cells of the first type on a model of an semiconductor device, and store the model of the semiconductor device including the plurality of the I/O cells of the first type in the computer readable storage medium.

    摘要翻译： 系统包括计算机可读存储介质和处理器。 计算机可读存储器包括表示用于建模和/或制造半导体器件的第一类型的输入/输出（“I / O”）单元的数据。 第一类型的I / O单元包括用于提供第一多个功能的电路。 处理器与计算机可读存储介质通信，并且被配置为选择第一类型的I / O单元，将第一类型的多个I / O单元布置在半导体器件的型号上，并存储 包括计算机可读存储介质中第一类型的多个I / O单元的半导体器件的型号。