BACKSIDE ILLUMINATED IMAGE SENSOR WITH NEGATIVELY CHARGED LAYER
    1.
    发明申请
    BACKSIDE ILLUMINATED IMAGE SENSOR WITH NEGATIVELY CHARGED LAYER 有权
    背面照明的图像传感器带负电荷层

    公开(公告)号:US20130285130A1

    公开(公告)日:2013-10-31

    申请号:US13743979

    申请日:2013-01-17

    IPC分类号: H01L27/146

    摘要: A semiconductor image sensor device having a negatively-charged layer includes a semiconductor substrate having a p-type region, a plurality of radiation-sensing regions in the p-type region proximate a front side of the semiconductor substrate, and a negatively-charged layer adjoining the p-type region proximate the plurality of radiation-sensing regions. The negatively-charged layer may be an oxygen-rich silicon oxide, a high-k metal oxide, or a silicon nitride formed as a liner in a shallow trench isolation feature, a sidewall spacer or an offset spacer of a transistor gate, a salicide-block layer, a buffer layer under a salicide-block layer, a backside surface layer, or a combination of these.

    摘要翻译: 具有带负电荷层的半导体图像传感器装置包括具有p型区域的半导体衬底,在靠近半导体衬底的前侧的p型区域中的多个辐射感测区域和带负电荷层 邻近多个辐射感测区域的p型区域。 带负电荷的层可以是在浅沟槽隔离特征,侧壁间隔物或晶体管栅极的偏移间隔物中形成的富氧氧化硅,高k金属氧化物或形成为衬垫的氮化硅,自对准硅 - 嵌段层,在自对流硅化物阻挡层下面的缓冲层,背面表面层或它们的组合。

    Method of Reducing Delamination in the Fabrication of Small-Pitch Devices
    2.
    发明申请
    Method of Reducing Delamination in the Fabrication of Small-Pitch Devices 有权
    减小小间距器件制造中分层的方法

    公开(公告)号:US20100136791A1

    公开(公告)日:2010-06-03

    申请号:US12326099

    申请日:2008-12-01

    IPC分类号: H01L21/308 H01L21/30

    CPC分类号: H01L21/0337

    摘要: A method of forming an integrated circuit structure includes providing a substrate; forming a first hard mask layer over the substrate; forming a second hard mask layer over the first hard mask layer; patterning the second hard mask layer to form a hard mask; and, after the step of patterning the second hard mask layer, baking the substrate, the first hard mask layer, and the hard mask. After the step of baking, a spacer layer is formed, which includes a first portion on a top of the hard mask, and a second portion and a third portion on opposite sidewalls of the hard mask. The method further includes removing the first portion of the spacer layer; removing the hard mask; and using the second portion and the third portion of the spacer layer as masks to pattern the first hard mask layer.

    摘要翻译: 形成集成电路结构的方法包括提供基板; 在衬底上形成第一硬掩模层; 在所述第一硬掩模层上形成第二硬掩模层; 图案化第二硬掩模层以形成硬掩模; 并且在图案化第二硬掩模层的步骤之后,烘烤基板,第一硬掩模层和硬掩模。 在烘烤步骤之后,形成间隔层,其包括在硬掩模的顶部上的第一部分和硬掩模的相对侧壁上的第二部分和第三部分。 该方法还包括去除间隔层的第一部分; 去除硬面膜; 并且使用间隔层的第二部分和第三部分作为掩模来对第一硬掩模层进行图案化。

    Method of forming a silicon nitride layer on a gate oxide film of a semiconductor device and annealing the nitride layer
    3.
    发明授权
    Method of forming a silicon nitride layer on a gate oxide film of a semiconductor device and annealing the nitride layer 有权
    在半导体器件的栅极氧化膜上形成氮化硅层并退火氮化物层的方法

    公开(公告)号:US07638442B2

    公开(公告)日:2009-12-29

    申请号:US12149906

    申请日:2008-05-09

    IPC分类号: H01L21/00

    CPC分类号: H01L21/28202 H01L21/28185

    摘要: A process for forming a silicon nitride layer on a gate oxide film as part of formation of a gate structure in a semiconductor device includes: forming a layer of silicon nitride on top of a gate oxide film on a semiconductor substrate by a nitridation process, heating the semiconductor substrate in an annealing chamber, exposing the semiconductor substrate to N2 in the annealing chamber, and exposing the semiconductor substrate to a mixture of N2 and N2O in the annealing chamber.

    摘要翻译: 在半导体器件中形成栅极结构的一部分,在栅极氧化膜上形成氮化硅层的工艺包括:通过氮化工艺在半导体衬底上的栅极氧化膜的顶部上形成氮化硅层,加热 在退火室中的半导体衬底,将半导体衬底暴露于退火室中的N2,并将半导体衬底暴露于退火室中的N 2和N 2 O的混合物。

    Method for processing residual gas
    4.
    发明授权
    Method for processing residual gas 失效
    残余气体的处理方法

    公开(公告)号:US07208127B2

    公开(公告)日:2007-04-24

    申请号:US10779634

    申请日:2004-02-18

    IPC分类号: B01D47/00

    摘要: A system for processing residual gas that includes a chamber having at least one baffle for increasing gas flow path, a residual gas inlet mechanism connected to the chamber for supplying residual gas to the chamber, at least one first gas inlet mechanism connected to the chamber for supplying inert gas to the chamber, at least one second gas inlet mechanism connected to the chamber for supplying a reactive gas to the chamber, and a gas outlet mechanism for connected to the chamber for outputting mixed gases from mixing the residual gas, inert gas and reactive gas and non-reacted residual gas, inert gas and reactive gas.

    摘要翻译: 一种用于处理残余气体的系统,其包括具有用于增加气体流路的至少一个挡板的室,连接到所述室的残余气体入口机构,用于向所述室供应残余气体;至少一个连接到所述室的第一气体入口机构, 向所述室供应惰性气体,连接到所述室的至少一个第二气体入口机构用于向所述室供应反应性气体;以及气体出口机构,用于连接到所述室,用于从混合残余气体,惰性气体和 反应气体和未反应的残留气体,惰性气体和反应气体。

    Method of reducing delamination in the fabrication of small-pitch devices
    6.
    发明授权
    Method of reducing delamination in the fabrication of small-pitch devices 有权
    减少小间距装置制造中分层的方法

    公开(公告)号:US08778807B2

    公开(公告)日:2014-07-15

    申请号:US13253694

    申请日:2011-10-05

    IPC分类号: H01L21/302

    CPC分类号: H01L21/0337

    摘要: A method of forming an integrated circuit structure includes providing a substrate; forming a first hard mask layer over the substrate; forming a second hard mask layer over the first hard mask layer; patterning the second hard mask layer to form a hard mask; and, after the step of patterning the second hard mask layer, baking the substrate, the first hard mask layer, and the hard mask. After the step of baking, a spacer layer is formed, which includes a first portion on a top of the hard mask, and a second portion and a third portion on opposite sidewalls of the hard mask. The method further includes removing the first portion of the spacer layer; removing the hard mask; and using the second portion and the third portion of the spacer layer as masks to pattern the first hard mask layer.

    摘要翻译: 形成集成电路结构的方法包括提供基板; 在衬底上形成第一硬掩模层; 在所述第一硬掩模层上形成第二硬掩模层; 图案化第二硬掩模层以形成硬掩模; 并且在图案化第二硬掩模层的步骤之后,烘烤基板,第一硬掩模层和硬掩模。 在烘烤步骤之后,形成间隔层,其包括在硬掩模的顶部上的第一部分和硬掩模的相对侧壁上的第二部分和第三部分。 该方法还包括去除间隔层的第一部分; 去除硬面膜; 并且使用间隔层的第二部分和第三部分作为掩模来对第一硬掩模层进行图案化。

    Method to form a CMOS image sensor
    7.
    发明授权
    Method to form a CMOS image sensor 有权
    形成CMOS图像传感器的方法

    公开(公告)号:US08759225B2

    公开(公告)日:2014-06-24

    申请号:US13602494

    申请日:2012-09-04

    IPC分类号: H01L21/311

    CPC分类号: H01L21/266 H01L27/14689

    摘要: The present disclosure relates to a method and composition to limit crystalline defects introduced in a semiconductor device during ion implantation. A high-temperature low dosage implant is performed utilizing a tri-layer photoresist which maintains the crystalline structure of the semiconductor device while limiting defect formation within the semiconductor device. The tri-layer photoresist comprises a layer of spin-on carbon deposited onto a substrate, a layer of silicon containing hard-mask formed above the layer of spin-on carbon, and a layer of photoresist formed above the layer of silicon containing hard-mask. A pattern formed in the layer of photoresist is sequentially transferred to the silicon containing hard-mask, then to the spin-on carbon, and defines an area of the substrate to be selectively implanted with ions.

    摘要翻译: 本发明涉及在离子注入期间限制在半导体器件中引入的结晶缺陷的方法和组合物。 使用保持半导体器件的晶体结构同时限制半导体器件内的缺陷形成的三层光致抗蚀剂进行高温低剂量注入。 三层光致抗蚀剂包括沉积在基底上的旋涂碳层,在旋涂碳层上方形成的含硅的硬掩模层,以及形成在含硅硬质层的硅层之上的光致抗蚀剂层, 面具。 形成在光致抗蚀剂层上的图案被顺序地转移到含硅的硬掩模,然后转移到旋涂碳上,并且限定要选择性地注入离子的衬底区域。

    ANTI-REFLECTIVE LAYER FOR BACKSIDE ILLUMINATED CMOS IMAGE SENSORS
    8.
    发明申请
    ANTI-REFLECTIVE LAYER FOR BACKSIDE ILLUMINATED CMOS IMAGE SENSORS 审中-公开
    用于背光照明的CMOS图像传感器的反反射层

    公开(公告)号:US20130270663A1

    公开(公告)日:2013-10-17

    申请号:US13755376

    申请日:2013-01-31

    IPC分类号: H01L27/146

    摘要: A method of forming an image sensor device includes forming a light sensing region at a front surface of a silicon substrate and a patterned metal layer there over. Thereafter, the method includes depositing a metal oxide anti-reflection laminate on the first surface of the substrate. The metal oxide anti-reflection laminate includes one or more composite layers of thin metal oxides stacked over the photodiode. Each composite layer includes two or more metal oxide layers: one metal oxide is a high energy band gap metal oxide and another metal oxide is a high refractive index metal oxide.

    摘要翻译: 形成图像传感器装置的方法包括在硅衬底的前表面上形成感光区域,并在其上形成图案化的金属层。 此后,该方法包括在基板的第一表面上沉积金属氧化物防反射层压板。 金属氧化物防反射层叠体包括层叠在光电二极管上的一层以上的金属氧化物复合层。 每个复合层包括两个或更多个金属氧化物层:一个金属氧化物是高能带隙金属氧化物,另一个金属氧化物是高折射率金属氧化物。

    METHOD OF FORMING A SILICON NITRIDE LAYER ON A GATE OXIDE FILM OF A SEMICONDUCTOR DEVICE AND ANNEALING THE NITRIDE LAYER
    9.
    发明申请
    METHOD OF FORMING A SILICON NITRIDE LAYER ON A GATE OXIDE FILM OF A SEMICONDUCTOR DEVICE AND ANNEALING THE NITRIDE LAYER 有权
    在半导体器件的栅极氧化膜上形成氮化硅层的方法和对硝酸盐层进行退火

    公开(公告)号:US20090280654A1

    公开(公告)日:2009-11-12

    申请号:US12149906

    申请日:2008-05-09

    IPC分类号: H01L21/31

    CPC分类号: H01L21/28202 H01L21/28185

    摘要: A process for forming a silicon nitride layer on a gate oxide film as part of formation of a gate structure in a semiconductor device includes: forming a layer of silicon nitride on top of a gate oxide film on a semiconductor substrate by a nitridation process, heating the semiconductor substrate in an annealing chamber, exposing the semiconductor substrate to N2 in the annealing chamber, and exposing the semiconductor substrate to a mixture of N2 and N2O in the annealing chamber.

    摘要翻译: 在半导体器件中形成栅极结构的一部分,在栅极氧化膜上形成氮化硅层的工艺包括:通过氮化工艺在半导体衬底上的栅极氧化膜的顶部上形成氮化硅层,加热 在退火室中的半导体衬底,将半导体衬底暴露于退火室中的N2,并将半导体衬底暴露于退火室中的N 2和N 2 O的混合物。