公开(公告)号：US07795090B2

公开(公告)日：2010-09-14

申请号：US12211815

申请日：2008-09-17

申请人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Pei-Ing Lee ,  Chung-Yuan Lee

发明人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Pei-Ing Lee ,  Chung-Yuan Lee

IPC分类号： H01L21/8242

CPC分类号： H01L29/66553 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/66621 ,  H01L29/66659

摘要： A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.

摘要翻译： 公开了一种使用不对称聚合间隔物制造自对准凹槽的方法。 提供了其上具有第一焊盘层和第二焊盘层的半导体衬底。 多个沟槽嵌入在半导体衬底的存储器阵列区域中。 每个沟槽包括从半导体衬底的主表面挤出的沟槽顶层。 非对称聚合物间隔物形成在挤出沟槽顶层的一侧上，并且在氧化之后用作用于在靠近沟槽形成凹部的掩模。

公开(公告)号：US07679137B2

公开(公告)日：2010-03-16

申请号：US11696163

申请日：2007-04-03

申请人： Pei-Ing Lee ,  Chien-Li Cheng ,  Shian-Jyh Lin

发明人： Pei-Ing Lee ,  Chien-Li Cheng ,  Shian-Jyh Lin

IPC分类号： H01L29/76 ,  H01L31/062

CPC分类号： H01L27/10861 ,  H01L27/0629 ,  H01L27/10876

摘要： A method of fabricating self-aligned gate trench utilizing TTO poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a trench top oxide (TTO) that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.

摘要翻译： 公开了一种使用TTO多隔离件制造自对准栅极沟槽的方法。 提供其上具有衬垫氧化物层和衬垫氮化物层的半导体衬底。 多个沟槽电容器嵌入在半导体衬底的存储器阵列区域中。 每个沟槽电容器具有从半导体衬底的主表面挤出的沟槽顶部氧化物（TTO）。 聚合物间隔物形成在挤出TTO的两个相对侧上，并且在氧化后用作蚀刻硬掩模，用于蚀刻紧邻沟槽电容器的凹陷栅极沟槽。

公开(公告)号：US07563686B2

公开(公告)日：2009-07-21

申请号：US11140889

申请日：2005-05-31

申请人： Pei-Ing Lee ,  Chung-Yuan Lee ,  Chien-Li Cheng

发明人： Pei-Ing Lee ,  Chung-Yuan Lee ,  Chien-Li Cheng

IPC分类号： H01L21/20

CPC分类号： H01L29/66621 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10876

摘要： A method for forming a memory device with a recessed gate is disclosed. A substrate with a pad layer thereon is provided. The pad layer and the substrate are patterned to form at least two trenches. A deep trench capacitor device is formed in each trench. The pad layer is recessed until upper portions of the deep trench capacitor devices are revealed. Spacers are formed on sidewalls of the upper portions of the deep trench capacitor devices. The pad layer and the substrate are etched using the spacers and the deep trench capacitor devices as a mask to form a recess, and a recessed gate is formed in the recess.

摘要翻译： 公开了一种用于形成具有凹入栅极的存储器件的方法。 提供其上具有垫层的衬底。 图案化衬垫层和衬底以形成至少两个沟槽。 在每个沟槽中形成深沟槽电容器器件。 衬垫层凹进直到深沟槽电容器器件的上部露出。 间隔件形成在深沟槽电容器器件的上部的侧壁上。 使用间隔物和深沟槽电容器器件作为掩模来蚀刻焊盘层和衬底以形成凹部，并且在凹部中形成凹入栅极。

公开(公告)号：US20090014768A1

公开(公告)日：2009-01-15

申请号：US11940547

申请日：2007-11-15

申请人： Shian-Jyh Lin ,  Chien-Li Cheng

发明人： Shian-Jyh Lin ,  Chien-Li Cheng

IPC分类号： H01L29/94 ,  H01L21/20

CPC分类号： H01L29/945 ,  H01L27/10823 ,  H01L27/10867 ,  H01L29/66181

摘要： A deep trench device with a single sided connecting structure. The device comprises a substrate having a trench therein. A buried trench capacitor is disposed in a lower portion of the trench. An asymmetric collar insulator is disposed on an upper portion of the sidewall of the trench. A connecting structure is disposed in the upper portion of the trench, comprising an epitaxial silicon layer disposed on and adjacent to a relatively low portion of the asymmetric collar insulator and a connecting member disposed between the epitaxial silicon layer and a relatively high portion of the asymmetric collar insulator. A conductive layer is disposed between the relatively high and low portions of the asymmetric collar insulator, to electrically connect the buried trench capacitor and the connecting structure. A cap layer is disposed on the connecting structure. A fabrication method for a deep trench device is also disclosed.

摘要翻译： 具有单面连接结构的深沟槽装置。 该装置包括其中具有沟槽的衬底。 埋沟槽电容器设置在沟槽的下部。 不对称环形绝缘体设置在沟槽的侧壁的上部。 连接结构设置在沟槽的上部，包括设置在不对称环形绝缘体的相对较低部分上并与其相邻的外延硅层，以及设置在外延硅层和不对称的较高部分之间的连接构件 项圈绝缘子。 导电层设置在不对称环形绝缘体的相对较高和较低的部分之间，以电连接埋入沟槽电容器和连接结构。 盖层设置在连接结构上。 还公开了一种深沟槽器件的制造方法。

公开(公告)号：US07473598B2

公开(公告)日：2009-01-06

申请号：US11738511

申请日：2007-04-22

申请人： Shian-Hau Liao ,  Tsung-Shin Wu ,  Chih-Chiang Kuo ,  Chien-Li Cheng

发明人： Shian-Hau Liao ,  Tsung-Shin Wu ,  Chih-Chiang Kuo ,  Chien-Li Cheng

IPC分类号： H01L21/8242 ,  H01L21/20 ,  H01L21/4763

CPC分类号： H01L28/91

摘要： A method for forming a stack capacitor includes providing a substrate with a bottom layer, a BPSG layer, a USG layer and a top layer thereon; using the top layer as a hard mask and the substrate as a first etching stop layer to perform a dry etching process to form a tapered trench in the bottom layer, the BPSG layer and the USG layer; removing the top layer to perform a selective wet etching process to partially remove the BPSG layer; depositing conformally a poly-Si layer and filling the trench with a sacrificial layer; removing the poly-Si layer unmasked by the sacrificial layer; using the bottom layer as a second etching stop layer to perform a wet etching process to remove the USG layer and BPSG layer; performing a static drying process; and depositing a dielectric layer and a conductive material to form the stack capacitor.

摘要翻译： 形成堆叠电容器的方法包括在其上提供具有底层，BPSG层，USG层和顶层的衬底; 使用顶层作为硬掩模，并且将基板作为第一蚀刻停止层，以执行干蚀刻工艺以在底层，BPSG层和USG层中形成锥形沟槽; 去除顶层以执行选择性湿蚀刻工艺以部分去除BPSG层; 沉积多晶硅层并用牺牲层填充沟槽; 去除由牺牲层未掩蔽的多晶硅层; 使用底层作为第二蚀刻停止层进行湿蚀刻工艺以去除USG层和BPSG层; 进行静态干燥过程; 以及沉积介质层和导电材料以形成堆叠电容器。

公开(公告)号：US20080251827A1

公开(公告)日：2008-10-16

申请号：US11776558

申请日：2007-07-12

申请人： Chien-Li Cheng ,  Chin-Tien Yang ,  Tzung-Han Lee ,  Shian-Hau Liao ,  Chung-Yuan Lee

发明人： Chien-Li Cheng ,  Chin-Tien Yang ,  Tzung-Han Lee ,  Shian-Hau Liao ,  Chung-Yuan Lee

IPC分类号： H01L27/108

CPC分类号： H01L27/0207 ,  H01L27/10885 ,  H01L27/10888 ,  Y10S257/905 ,  Y10S257/906

摘要： A checkerboard deep trench dynamic random access memory cell array layout is disclosed, which includes a substrate, a plurality of gate conductor lines disposed on the substrate, a plurality of checkerboard-arranged and staggered deep trench capacitor structures embedded in the substrate under the gate conductor lines, and a plurality of active areas formed in the substrate under the gate conductor lines, alternatively arranged with the deep trench capacitor structures, and electrically connected with an adjacent deep trench capacitor structure. The width of the parts of the gate conductor lines above the deep trench capacitor structures is narrower than that of the parts of the gate conductor lines above the active areas.

摘要翻译： 公开了一种棋盘深沟动态随机存取存储单元阵列布局，其包括衬底，设置在衬底上的多个栅极导体线，嵌入在栅极导体下方的衬底中的多个棋盘布置且交错的深沟槽电容器结构 线路，以及形成在栅极导体线下方的基板中的多个有源区域，交替布置有深沟槽电容器结构，并与相邻的深沟槽电容器结构电连接。 深沟槽电容器结构之上的栅极导体线的部分的宽度比在有源区上方的栅极导体线的部分的宽度窄。

公开(公告)号：US20070032085A1

公开(公告)日：2007-02-08

申请号：US11195293

申请日：2005-08-02

申请人： Pei-Ing Lee ,  Chung-Yuan Lee ,  Chien-Li Cheng

发明人： Pei-Ing Lee ,  Chung-Yuan Lee ,  Chien-Li Cheng

IPC分类号： H01L21/311 ,  H01L21/302

CPC分类号： H01L21/3086 ,  H01L21/26586 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10876 ,  H01L29/66621 ,  Y10S438/944 ,  Y10S438/947

摘要： A method for forming a recess. The method includes providing a substrate with two protrusions having a first side wall and a second side wall opposite to the first side wall disposed above the substrate, conformally forming a mask layer on the substrate and the protrusions, tilt implanting the mask layer with a first angle using a first implanting mask adjacent to the first side wall of the protrusions, tilt implanting the mask layer with a second angle using a second implanting mask adjacent to the second side wall of the protrusions, removing implanted portions of the mask layer to form a patterned mask layer, and etching the substrate using the patterned mask layer, thereby forming a recess, wherein distances from the recess to the two protrusions, respectively, are different.

摘要翻译： 一种形成凹部的方法。 该方法包括提供具有两个突出物的两个突起，所述两个突起具有第一侧壁和与设置在基底上方的第一侧壁相对的第二侧壁，在基底上共形成掩模层和突起，倾斜地将掩模层以第一 使用与突起的第一侧壁相邻的第一注入掩模的角度，使用与突起的第二侧壁相邻的第二注入掩模以第二角度注入掩模层，去除掩模层的植入部分以形成 图案化掩模层，并使用图案化掩模层蚀刻基板，从而形成凹部，其中分别从凹部到两个突起的距离不同。

公开(公告)号：US20070032038A1

公开(公告)日：2007-02-08

申请号：US11195294

申请日：2005-08-02

申请人： Pei-Ing Lee ,  Chung-Yuan Lee ,  Chien-Li Cheng

发明人： Pei-Ing Lee ,  Chung-Yuan Lee ,  Chien-Li Cheng

IPC分类号： H01L21/76

CPC分类号： H01L21/3086 ,  H01L21/26586 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10876 ,  H01L29/66621 ,  Y10S438/944 ,  Y10S438/947

摘要： A method for forming a recess. The method includes providing a substrate with two protrusions having a first side wall and a second side wall opposite to the first side wall disposed above the substrate, conformally forming a mask layer on the substrate and the protrusions, tilt implanting the mask layer using a first implanting mask adjacent to the first side wall of the protrusions, removing implanted portions of the mask layer to form a patterned mask layer, and etching the substrate using the patterned mask layer, thereby forming a recess.

摘要翻译： 一种形成凹部的方法。 该方法包括提供具有两个突起的基底，该突起具有第一侧壁和与设置在基底上方的第一侧壁相对的第二侧壁，在基底上保形地形成掩模层和突起，使用第一 将掩模与所述突起的第一侧壁相邻地植入，去除所述掩模层的注入部分以形成图案化掩模层，并且使用所述图案化掩模层蚀刻所述衬底，从而形成凹部。

公开(公告)号：US07897501B2

公开(公告)日：2011-03-01

申请号：US12013528

申请日：2008-01-14

申请人： Chien-Li Cheng ,  Sun-Jay Chang ,  Tung-Heng Hsieh ,  Yung-Shen Chen

发明人： Chien-Li Cheng ,  Sun-Jay Chang ,  Tung-Heng Hsieh ,  Yung-Shen Chen

IPC分类号： H01L21/4763

CPC分类号： H01L29/6656 ,  H01L29/665 ,  H01L29/6653

摘要： A method of fabricating a semiconductor device is disclosed. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a gate stack overlying the semiconductor substrate; forming spacers each having a first inner spacer and a second outer spacer on sidewalls of the gate stack; forming a protective layer on sidewalls of the spacers, covering a part of the semiconductor substrate, wherein an etching selectivity of the protective layer is higher than that of the first inner spacer.

摘要翻译： 公开了制造半导体器件的方法。 制造半导体器件的方法提供半导体衬底; 形成覆盖在半导体衬底上的栅叠层; 每个在所述栅极叠层的侧壁上具有第一内隔离物和第二外隔离物的隔离物; 在所述间隔物的侧壁上形成保护层，覆盖所述半导体衬底的一部分，其中所述保护层的蚀刻选择性高于所述第一内衬垫的蚀刻选择性。

公开(公告)号：US20100012179A1

公开(公告)日：2010-01-21

申请号：US12372975

申请日：2009-02-18

申请人： Chien-Li Cheng

发明人： Chien-Li Cheng

IPC分类号： H01L31/00 ,  H01L21/3105 ,  H01L21/02

CPC分类号： H01L31/022425 ,  H01L31/02168 ,  H01L31/022466 ,  Y02E10/50

摘要： A solar cell with high photon utilization includes a substrate, a transparent conductive oxide layer, an anti-reflection coating (ARC) layer and at least one main charge collecting line. The substrate has a front side and a back side. The substrate has a first-type semiconductor layer close to the back side and a second-type semiconductor layer close to the front side. The transparent conductive oxide layer is formed on the front side. The ARC layer is formed on the transparent conductive oxide layer. The main charge collecting line penetrates through the ARC layer and projects from the ARC layer, and the main charge collecting line is electrically connected to the transparent conductive oxide layer. A method of manufacturing the solar cell is also disclosed.

摘要翻译： 具有高光子利用率的太阳能电池包括基板，透明导电氧化物层，抗反射涂层（ARC）层和至少一个主电荷收集线。 基板具有前侧和后侧。 衬底具有靠近背面的第一类型半导体层和靠近正面的第二类型半导体层。 透明导电氧化物层形成在前侧。 ARC层形成在透明导电氧化物层上。 主电荷收集线穿过ARC层并从ARC层突出，并且主电荷收集线电连接到透明导电氧化物层。 还公开了一种制造太阳能电池的方法。