Abstract:
A package stack device includes a first package structure having a plurality of first metal posts and a first electronic element disposed on a surface thereof, a second package structure having a plurality of second metal posts and a second electronic element disposed on opposite surfaces thereof, and an encapsulant formed between the first and second package structures for encapsulating the first electronic element. By connecting the first and second metal posts, the second package structure is stacked on the first package structure with the support of the metal posts and the encapsulant filling the gap therebetween so as to prevent warpage of the substrate.
Abstract:
A mobile terminal includes a base body, a pair of slidable bodies and a pair of switch mechanisms disposed on the slidable bodies. Each of the switch mechanism includes a housing, a cover, an operating member, a locking member and a spring unit. The operating member includes a coupling portion received in the housing and an operating cap located out of the housing. The coupling portion includes a base bevel. The locking member received in the housing includes a sliding bevel contacting to the base bevel and a locking block passing through the cover and engaging with the base body. The spring unit urges between the locking member and the housing. When the operating cap is pressed towards the housing, the base bevel engages with the sliding bevel to drive the locking member compress the spring unit, thereby the locking block disengaging from the base body.
Abstract:
User-defined interface editing methods for mobile electronic devices. Display-related information of an interface is edited as modified information in an interface editor. The modified information is transmitted from the interface editor to the mobile electronic device. The interface is displayed on the mobile electronic device according to the modified information after parsing.
Abstract:
A substrate for a pre-soldering material and a fabrication method of the substrate are proposed. The substrate having at least one surface formed with a plurality of conductive pads is provided. An insulating layer is formed over the surface of the substrate in such a way that a top surface of each of the conductive pads is exposed. Next, a conductive film and a resist layer are formed in sequence on the insulating layer and the conductive pads, wherein a plurality of openings are formed in the resist layer to expose a part of the conductive film above the conductive pad. Then, a pre-soldering material is deposited over the conductive pad by stencil printing or electroplating process.
Abstract:
A substrate for a pre-soldering material and a fabrication method of the substrate are proposed. The substrate having at least one surface formed with a plurality of conductive pads is provided. An insulating layer is formed over the surface of the substrate in such a way that a top surface of each of the conductive pads is exposed. Next, a conductive film and a resist layer are formed in sequence on the insulating layer and the conductive pads, wherein a plurality of openings are formed in the resist layer to expose a part of the conductive film above the conductive pad. Then, a pre-soldering material is deposited over the conductive pad by stencil printing or electroplating process.
Abstract:
An image data processing method is provided. In this method, a plurality of original pixel values of an image is input. An interpolation position of a target pixel in the image is determined. Whether the interpolation position is in a central region of an object or in a marginal region of an object is determined. A pixel value interpolation with respect to the interpolation position is performed. When the interpolation position is in the central region of an object, the pixel value interpolation is performed in a first calculation mode, and when the interpolation position is in the marginal region of an object, the pixel value interpolation is performed in a second calculation mode, wherein the first calculation mode may be a low pass filtering interpolation mode, and the second calculation mode may be a linear interpolation mode.
Abstract:
A direct connection multi-chip semiconductor element structure is proposed. A plurality of semiconductor chips are mounted and supported on a metal heat sink, such that heat generated by the chips during operation can be dissipated via the heat sink. A circuit structure is extended from the chips to provide direct electrical extension for the chips and improve the electrical performances. And exposed electrical connection terminals can be formed in the circuit structure extended from the chips to be directly electrically connected to an external electronic device.
Abstract:
A chair includes a base which includes two facing sides and each of the facing sides has two grooves and both of which extend in a horizontal direction and a vertical direction. A seat has four engaging members which are movably engaged with the four grooves in the two facing sides of the base so that the seat can be moved in horizontal and vertical directions relative to the base.
Abstract:
A circuit board structure with an embedded semiconductor chip and a fabrication method thereof are provided, including the steps of providing a semiconductor wafer having an active surface with a plurality of electrode pads, a connection metal layer formed on the electrode pads: forming a protective layer on the connection metal layer and the semiconductor wafer, performing a cutting process to form a plurality of semiconductor dies, providing a carrier board having at least on e cavity for receiving the semiconductor chip; and forming sequentially on the protective layer covering the semiconductor chip and the carrier board a dielectric layer and a circuit layer electrically connected to the connection metal layer of the semiconductor chip. The present invention is a simple, in process and low in process cost, due to the connection metal layer covered by the protective layer formed on the semiconductor chip protected from oxidation and contamination.
Abstract:
A wafer and single chip having a circuit rearranged structure and method for fabricating the same are proposed. A wafer having a plurality of chips is provided. Each of the chip has an active surface having a plurality of electrode pads. A dielectric layer is formed on the active surface. The dielectric layer is thinned to expose the electrode pads. A conducting layer is formed on the dielectric layer and the electrode pads. A first metal layer is formed on the conductive layer by electroplating. A patterned second metal layer is formed on the first metal layer by printing. Using the second metal layer as a protecting layer, the first metal layer and the conducting layer are etched and part uncovered by the second metal layer are removed. The second and the remaining first metal layer form a circuit rearranged structure electrically connected to the electrode pads.