公开(公告)号：US09424942B2

公开(公告)日：2016-08-23

申请号：US14639341

申请日：2015-03-05

申请人： Dong-Kyo Shim

发明人： Dong-Kyo Shim

IPC分类号： G11C16/26 ,  G11C16/10 ,  G11C16/24 ,  G11C11/56 ,  G11C16/34 ,  G11C29/04

CPC分类号： G11C16/26 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3454 ,  G11C2029/0411

摘要： A non-volatile memory device includes a memory cell array having a plurality of memory cells programmable into one of multiple logic states, the plurality of memory cells disposed at intersections of a plurality of wordlines and a plurality of bitlines, and a plurality of page buffers respectively connected to the plurality of bitlines and performing verifying read operations on the plurality of memory cells. The verifying read operations are performed on a first memory cell having a target state and a second memory cell having a lower state than the target state.

摘要翻译： 一种非易失性存储器件包括具有可编程为多个逻辑状态之一的多个存储单元的存储单元阵列，多个存储单元设置在多个字线和多个位线的交点处，以及多个页缓冲器 分别连接到多个位线，并对多个存储器单元执行验证读取操作。 在具有目标状态的第一存储单元和具有比目标状态低的状态的第二存储单元中执行验证读操作。

公开(公告)号：US20170125128A1

公开(公告)日：2017-05-04

申请号：US15207774

申请日：2016-07-12

申请人： JI-SANG LEE ,  SANG-SOO PARK ,  DONG-KYO SHIM

发明人： JI-SANG LEE ,  SANG-SOO PARK ,  DONG-KYO SHIM

IPC分类号： G11C29/56 ,  G11C8/10 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C7/10

CPC分类号： G11C29/1201 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/12 ,  G11C7/14 ,  G11C7/222 ,  G11C8/10 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C27/02 ,  G11C29/42 ,  G11C29/50012 ,  G11C29/52 ,  G11C29/56008 ,  G11C2029/0411 ,  G11C2029/5004 ,  G11C2211/5642

摘要： A nonvolatile memory device with a memory cell array including a plurality of memory cells coupled to first through M-th wordlines and first through N-th bitlines (M>2, N>2), and a page buffer circuit including first through N-th page buffers that are coupled to the first through N-th bitlines, respectively, and generate first through N-th output data, respectively. A K-th page buffer includes first through L-th latches which generate read data by sampling a voltage of a K-th output line, which is discharged through a K-th bitline, at different sampling timings after a read voltage is applied to a P-th wordline (K≦N, L>1, P≦M). The K-th page buffer outputs the first output data if an error in the read data of the first latch is correctable.

公开(公告)号：US20170123724A1

公开(公告)日：2017-05-04

申请号：US15336014

申请日：2016-10-27

申请人： SANG-SOO PARK ,  DONG-KYO SHIM

发明人： SANG-SOO PARK ,  DONG-KYO SHIM

IPC分类号： G06F3/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C16/16

CPC分类号： G06F3/0656 ,  G06F3/0604 ,  G06F3/0685 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/3459 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2211/5644

摘要： A memory device is provided as follows. A memory cell array includes a plurality of memory cells, and the plurality of memory cells are divided into a first memory group and a second memory group. A first page buffer group is coupled to the first memory group and includes a plurality of first page buffers. A second page buffer group is coupled to the second memory group and includes a plurality of second page buffers. The first page buffer group performs a first data processing operation on data stored in the first page buffer group and stores a result of the first data processing operation. The second page buffer group performs a second data processing operation on data stored in the second page buffer group and stores a result of the second data processing operation. The first and second data processing operations are performed at substantially the same.

公开(公告)号：US20160005490A1

公开(公告)日：2016-01-07

申请号：US14639341

申请日：2015-03-05

申请人： DONG-KYO SHIM

发明人： DONG-KYO SHIM

IPC分类号： G11C16/34 ,  G11C16/24 ,  G11C16/26 ,  G11C16/10

CPC分类号： G11C16/26 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3454 ,  G11C2029/0411

摘要： A non-volatile memory device includes a memory cell array having a plurality of memory cells programmable into one of multiple logic states, the plurality of memory cells disposed at intersections of a plurality of wordlines and a plurality of bitlines, and a plurality of page buffers respectively connected to the plurality of bitlines and performing verifying read operations on the plurality of memory cells, The verifying read operations are performed on a first memory cell having a target state and a second memory cell having a lower state than the target state.

摘要翻译： 一种非易失性存储器件包括具有可编程为多个逻辑状态之一的多个存储单元的存储单元阵列，多个存储单元设置在多个字线和多个位线的交点处，以及多个页缓冲器 分别连接到多个位线并对多个存储器单元执行验证读取操作。在具有目标状态的第一存储单元和具有比目标状态低的状态的第二存储单元执行验证读操作。