公开(公告)号：US5528190A

公开(公告)日：1996-06-18

申请号：US316958

申请日：1994-10-03

申请人： Edward H. Honnigford

发明人： Edward H. Honnigford

IPC分类号： H03K5/08 ,  H03K17/16

CPC分类号： H03K17/162 ,  H03K5/08

摘要： A voltage clamping circuit is provided for clamping the input voltage to CMOS devices near the rail voltages so as to prevent forward biased junctions, minority carrier injection and crosstalk between voltage inputs. The voltage clamping circuit receives an input voltage and provides an output voltage within a rail-to-rail voltage range. The clamping circuit has a bias circuit with a PMOS device for providing a p-channel threshold drop to an upper rail voltage so as to generate an upper threshold bias voltage. The bias circuit also has an NMOS device for providing an n-channel threshold increase to a lower rail voltage so as to generate a lower threshold bias voltage. A first clamping transistor is coupled to the input for clamping the input voltage so as to prevent the input voltage from rising above the upper rail voltage. A second clamping transistor is coupled to the input for clamping the input voltage so as to prevent the input voltage from dropping below the lower rail voltage. Gain stages control the clamping transistors in response to the upper and lower threshold bias voltages and the input voltage so as to cause the clamping transistors to clamp the input voltage.

摘要翻译： 提供了一个钳位电路，用于将输入电压钳位在靠近轨道电压的CMOS器件上，以防止正向偏置接合，少数载流子注入和电压输入之间的串扰。 电压钳位电路接收输入电压并在轨至轨电压范围内提供输出电压。 钳位电路具有带PMOS器件的偏置电路，用于向上轨道电压提供p沟道阈值电压，以产生上阈值偏置电压。 偏置电路还具有用于向较低轨电压提供n沟道阈值增加以产生较低阈值偏置电压的NMOS器件。 第一钳位晶体管耦合到输入端，用于钳位输入电压，以防止输入电压升高到高于上轨道电压。 第二钳位晶体管耦合到输入端，用于钳位输入电压，以防止输入电压降到低于下轨道电压。 增益级响应于上限和下限阈值偏置电压和输入电压来控制钳位晶体管，以便使钳位晶体管钳位输入电压。

公开(公告)号：US4527074A

公开(公告)日：1985-07-02

申请号：US433292

申请日：1982-10-07

申请人： Darrel D. Donaldson ,  Edward H. Honnigford ,  Alan D. Poeppelman

发明人： Darrel D. Donaldson ,  Edward H. Honnigford ,  Alan D. Poeppelman

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  H03K17/06 ,  H03K17/687

CPC分类号： G11C16/30 ,  G11C16/12 ,  G11C16/16 ,  G11C16/32 ,  H03K17/06

摘要： An electronic circuit configured to pass relatively high voltage signals therethrough when enabled, and block both positive and negative signals when appropriately disabled. The features of the circuit are particularly suited for coupling write and erase voltages to a nonvolatile memory array while integrated on a common chip with the array. In one form, the circuit includes a two-phase pump, which upon being enabled draws a transient current from the high voltage input line and raises the voltage level on an internal capacitive node in closed loop fashion by effecting unidirectional transfers of charge between successive capacitive nodes. The elevated internal voltage provides a driving signal to a driving circuit which passes the high voltage on the input line to an output line without incurring threshold voltage losses.

摘要翻译： 一种电子电路，被配置为当使能时通过相对较高的电压信号，并且在适当地禁用时阻止正和负信号。 电路的特征特别适用于将写入和擦除电压耦合到非易失性存储器阵列，同时集成在具有阵列的公共芯片上。 在一种形式中，该电路包括一个两相泵，其在启用时从高电压输入线吸入瞬态电流，并以闭环方式提升内部电容性节点上的电压电平，这是通过在连续电容 节点。 升高的内部电压向驱动电路提供驱动信号，该驱动电路将输入线路上的高电压传递到输出线路，而不会引起阈值电压损耗。

公开(公告)号：US5369319A

公开(公告)日：1994-11-29

申请号：US992306

申请日：1992-12-21

申请人： Brian K. Good ,  Gregory J. Manlove ,  Edward H. Honnigford

发明人： Brian K. Good ,  Gregory J. Manlove ,  Edward H. Honnigford

IPC分类号： H03K3/011 ,  H03K3/0233 ,  H03K3/3565 ,  H03K5/22

CPC分类号： H03K3/3565 ,  H03K3/011 ,  H03K3/02337

摘要： A MOS hysteresis comparator having a source transistor bias circuit which generates a source current Is that compensates for temperature and manufacturing process variations, thereby providing a hysteresis characteristic which is substantially insensitive to such temperature and manufacturing process variations. The source transistor bias circuit includes a set of MOS transistors which replicate the comparator load currents which occur at the switch points of the comparator, and a source transistor which mirrors the sum of the replicated currents to form the source current Is of the comparator.

摘要翻译： MOS滞后比较器具有源极晶体管偏置电路，其产生补偿温度和制造工艺变化的源电流Is，从而提供对这种温度和制造工艺变化基本上不敏感的滞后特性。 源晶体管偏置电路包括一组MOS晶体管，其复制在比较器的开关点处发生的比较器负载电流，以及源晶体管，其反映复制电流的和以形成比较器的源电流Is。

公开(公告)号：US4534104A

公开(公告)日：1985-08-13

申请号：US352734

申请日：1982-02-26

申请人： Vinod K. Dham ,  Edward H. Honnigford ,  John K. Stewart, Jr. ,  Robert F. Pfeifer ,  Murray L. Trudel

发明人： Vinod K. Dham ,  Edward H. Honnigford ,  John K. Stewart, Jr. ,  Robert F. Pfeifer ,  Murray L. Trudel

IPC分类号： H01L21/8246 ,  H01L27/088 ,  H01L29/423 ,  H01L21/22 ,  H01L21/26

CPC分类号： H01L27/1126 ,  H01L27/088 ,  H01L29/42368

摘要： A process for fabricating volatile and nonvolatile field effect devices on a common semiconductor wafer, and a unique composite structure for a nonvolatile memory device fabricated according to the process. A distinct feature of the process is the elimination of nitride from beneath any poly I layers while selectively retaining sandwiched and coextensive segments of nitride and poly II layers for the memory devices. In one form, the method commences with a wafer treated according to the general localized oxidation of silicon process, followed by a blanket enhancement implant and selectively masked depletion implants. The succeeding contact etch step is followed by a deposition of a poly I layer, a resistor forming implant and a patterned etch of the poly I layer. Thereafter, a first isolation oxide is grown, selective implants are performed to center the memory window, the memory area is etched, and the memory area is covered by a regrowth of a very thin memory oxide. The wafer is then coated with nitride and poly II, before undergoing a patterned plasma etch which successively and coextensively removes poly II and nitride in unwanted areas. Consequently, any nitride which remains is in a sandwiched arrangement with an overlying layer of poly II. The process inherently retains no nitride under any poly I layer, and thereby enhances the reliability of the complete IC. The composite nonvolatile memory device includes a poly II nonvolatile memory capacitor, a poly II depletion IGFET, and a poly I depletion IGFET over a single continuum of channel. The structural arrangement provides for selective access to the nonvolatile memory capacitor through the poly I IGFET during the write mode.

摘要翻译： 用于在公共半导体晶片上制造易失性和非易失性场效应器件的工艺，以及用于根据该工艺制造的非易失性存储器件的唯一复合结构。 该方法的一个显着特征是从任何多晶硅层下面消除氮化物，同时选择性地保留用于存储器件的夹层和共延伸的氮化物和聚二层的层。 在一种形式中，该方法开始于根据硅工艺的一般局部氧化进行处理的晶片，随后进行覆盖增强植入和选择性掩蔽的耗尽植入物。 接下来的接触蚀刻步骤之后是多晶I层，电阻器形成注入的沉积和多晶I层的图案化蚀刻。 此后，生长第一隔离氧化物，执行选择性植入物以使存储窗口居中，存储区域被蚀刻，并且存储区域被非常薄的记忆氧化物的再生长所覆盖。 然后在经历图案化等离子体蚀刻之前用氮化物和聚合物II涂覆晶片，其连续地并共同地除去不需要的区域中的聚II和氮化物。 因此，残留的任何氮化物与聚II的上覆层夹在中间。 该工艺本身就不会在任何多晶硅层下保留氮化物，从而提高了整个IC的可靠性。 复合非易失性存储器件包括多通道非易失性存储器电容器，多晶II耗尽型IGFET和多通道消耗型IGFET通过单个连续的通道。 结构布置提供了在写入模式期间通过poly I IGFET选择性地访问非易失性存储器电容器。

公开(公告)号：US5530388A

公开(公告)日：1996-06-25

申请号：US409249

申请日：1995-03-24

申请人： Edward H. Honnigford

发明人： Edward H. Honnigford

IPC分类号： H03K4/04

CPC分类号： H03K4/04

摘要： A parabolic current generator is provided for use with a waveshaping circuit for producing a sinusoidally increasing bus output voltage signal in response to the rising edge of a data input signal, and a sinusoidally decreasing bus output voltage signal in response to a falling edge of the data input signal. The parabolic current generator provides a current that increases parabolically in response to the rising or falling edge of the data input signal and that decreases parabolically when the bus output voltage signal reaches one-half of its intended full voltage swing or falls below one-half of the full voltage swing to respectively produce the sinusoidally increasing and decreasing voltage at the bus output. The parabolic current generator includes an operational amplifier having an integrating capacitor connected between its non-inverting input and its output. A field effect transistor is connected to its inverting input and has an impedance sized to minimize the capacitor value.

摘要翻译： 提供抛物线电流发生器用于波形整形电路，用于响应于数据输入信号的上升沿产生正弦增加的总线输出电压信号，以及响应于数据的下降沿的正弦递减的总线输出电压信号 输入信号。 抛物线电流发生器提供响应于数据输入信号的上升沿或下降沿抛物线增加的电流，并且当总线输出电压信号达到其预期的全部电压摆幅的一半或低于其一半 全电压摆幅分别在总线输出端产生正弦增减电压。 抛物线电流发生器包括具有连接在其非反相输入和其输出之间的积分电容器的运算放大器。 场效应晶体管连接到其反相输入端并具有阻抗大小以使电容器值最小化。

公开(公告)号：US5408133A

公开(公告)日：1995-04-18

申请号：US55593

申请日：1993-05-03

申请人： Edward H. Honnigford ,  William J. Hulka

发明人： Edward H. Honnigford ,  William J. Hulka

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  H03K4/06 ,  H03K17/56

CPC分类号： G11C16/12 ,  G11C16/10

摘要： An apparatus for providing an EEPROM programming signal, comprises a charge pump circuit for receiving a programming input signal on a programming input line and for charging up a gate drive voltage signal in response to a rising edge of the programming input signal. A transistor that includes a gate coupled to the gate drive signal couples the programming input line to a programming output line, which is coupled to an EEPROM. A ramp control circuit including (i) a capacitor and (ii) a transistor controlling the flow of current through the capacitor, is coupled to the programming output line for regulating a ramp-up rate of a programming output signal on the programming output line. A ramp-down circuit is coupled to the programming input line and to the programming output line and is responsive thereto for providing a ramp-down of the programming output signal after the programming input signal goes low.

摘要翻译： 一种用于提供EEPROM编程信号的装置，包括用于在编程输入线上接收编程输入信号并且响应于编程输入信号的上升沿对门驱动电压信号充电的电荷泵电路。 包括耦合到栅极驱动信号的栅极的晶体管将编程输入线耦合到编程输出线，该编程输出线耦合到EEPROM。 包括（i）电容器和（ii）控制通过电容器的电流的晶体管的斜坡控制电路被耦合到编程输出线，用于调节编程输出线上的编程输出信号的上升速率。 斜坡下降电路耦合到编程输入线和编程输出线，并响应于此，在编程输入信号变为低电平之后提供编程输出信号的斜降。

公开(公告)号：US5371500A

公开(公告)日：1994-12-06

申请号：US944145

申请日：1992-09-11

申请人： Raymond Lippmann ,  James E. Nelson ,  Michael J. Schnars ,  James R. Chintyan ,  Mark C. Hansen ,  Edward H. Honnigford

发明人： Raymond Lippmann ,  James E. Nelson ,  Michael J. Schnars ,  James R. Chintyan ,  Mark C. Hansen ,  Edward H. Honnigford

IPC分类号： G06J1/00 ,  H03M1/06 ,  H03M1/08 ,  H03M1/12 ,  H03M1/66 ,  H03M1/78

CPC分类号： H03M1/0619 ,  G06J1/00 ,  H03M1/0845 ,  H03M1/12 ,  H03M1/66

摘要： A circuit apparatus comprises interface circuitry between analog and digital circuitry. A multiple reference circuit provides a variety of reference voltage signals. The multiple reference circuitry is coupled to a selection circuit that selectively couples one of the reference voltage signals to a first reference input of the interface circuitry and selectively couples another of the reference voltage signals to a second reference input of the interface circuitry, whereby the first and second reference inputs may be selectively coupled to the reference voltages and the circuit maintains a ratiometric relationship between the digital and analog circuitry.

摘要翻译： 电路装置包括模拟和数字电路之间的接口电路。 多参考电路提供各种参考电压信号。 多个参考电路耦合到选择电路，选择电路将参考电压信号中的一个选择性地耦合到接口电路的第一参考输入，并将另一个参考电压信号选择性地耦合到接口电路的第二参考输入，由此第一 并且第二参考输入可以选择性地耦合到参考电压，并且电路维持数字和模拟电路之间的比例关系。

公开(公告)号：US5367249A

公开(公告)日：1994-11-22

申请号：US048847

申请日：1993-04-21

申请人： Edward H. Honnigford

发明人： Edward H. Honnigford

IPC分类号： G05F3/20 ,  G05F3/16

CPC分类号： G05F3/20 ,  Y10S323/901

摘要： An apparatus comprises a bandgap reference voltage circuit with first and second current legs and circuitry for generating a bandgap reference voltage. A transistor is coupled to the first current leg for selectively providing current to the first leg of the bandgap reference voltage circuit. A control circuit controls the transistor to turn the transistor on when an external voltage supply is initially applied to the apparatus to provide a start up current to the bandgap voltage reference source and senses an output voltage developed by the bandgap reference current source. The control circuit turns off the transistor responsive to the sensed developed voltage when the sensed developed voltage rises above a predetermined threshold.

摘要翻译： 一种装置包括具有第一和第二电流支路的带隙参考电压电路和用于产生带隙参考电压的电路。 晶体管耦合到第一电流支路，用于选择性地将电流提供给带隙基准电压电路的第一支路。 控制电路控制晶体管，以便当外部电压源最初被施加到该装置以使提供到带隙电压参考源的启动电流并感测由带隙参考电流源产生的输出电压时，晶体管导通。 当感测到的显影电压升高到高于预定阈值时，控制电路响应感测到的显影电压而关断晶体管。

公开(公告)号：US5365200A

公开(公告)日：1994-11-15

申请号：US957837

申请日：1992-10-08

申请人： Edward H. Honnigford ,  Gregory J. Manlove

发明人： Edward H. Honnigford ,  Gregory J. Manlove

IPC分类号： H03F3/345 ,  H03F3/45 ,  H03F1/34 ,  G01R1/30

CPC分类号： H03F3/345 ,  H03F3/45076

摘要： An integrated circuit apparatus comprises a first stage amplifier and a second stage amplifier. The first stage amplifier is characterized by a cross-coupled integrated layout providing a rail-to-rail swing and a linear gain, A, substantially defined as A=g.sub.m r.sub.o '. The second stage amplifier is coupled to the output of the first stage amplifier and comprises a high-voltage integrated circuit transistor with an AC feedback circuit, the AC feedback circuit comprising, in series, a capacitor, a N+ resistor and an N-WELL resistor, wherein the output of the second stage amplifier is used to directly drive an inductive load.

摘要翻译： 集成电路装置包括第一级放大器和第二级放大器。 第一级放大器的特征在于交叉耦合集成布局，提供轨至轨摆幅和线性增益A，基本上定义为A = gmro'。 第二级放大器耦合到第一级放大器的输出，并且包括具有AC反馈电路的高压集成电路晶体管，AC反馈电路串联包括电容器，N +电阻器和N-WELL电阻器 ，其中第二级放大器的输出用于直接驱动感性负载。

公开(公告)号：US4397076A

公开(公告)日：1983-08-09

申请号：US301557

申请日：1981-09-14

申请人： Edward H. Honnigford ,  Vinod K. Dham

发明人： Edward H. Honnigford ,  Vinod K. Dham

IPC分类号： H01L21/3205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L29/78 ,  H01L21/22 ,  H01L21/265

CPC分类号： H01L21/28525

摘要： A process for making buried contacts without damaging the surface of the silicon substrate while etching the pattern of a poly interconnect layer. The contact cut made in the gate oxide layer covering the substrate is made smaller than the poly deposited and patterned thereover. Damage to the substrate surface during the etching of the poly layer pattern is prevented by the presence of the gate oxide layer between the poly layer and the substrate. An ion implantation step performed early in the process forms a parasitic depletion mode channel under the region having an overlap of poly onto gate oxide. Consequently, though the gate oxide prevents the direct diffusion of dopant into the underlying substrate when conductors are formed by doping, the parasitic channel ohmically couples the poly interconnect layer to the diffused region in the substrate. The latter region is usually the S/D electrode of an IGFET. The composite process is compatible with the formation of self-aligned gates and conductively doped poly and substrate regions which are simultaneously doped with the same impurity.

摘要翻译： 一种用于在蚀刻多晶硅互连层的图案的同时在不损坏硅衬底的表面的情况下进行掩埋接触的工艺。 在覆盖基板的栅极氧化物层中形成的接触切割比在其上沉积和图案化的多。 在多层图案的蚀刻过程中，衬底表面的损伤通过在多层和衬底之间存在栅极氧化层来防止。 在该过程中早期进行的离子注入步骤在具有多晶重叠到栅极氧化物的区域之下形成寄生耗尽模式沟道。 因此，尽管当通过掺杂形成导体时，栅极氧化物防止掺杂剂直接扩散到下面的衬底中，但是寄生沟道将多晶硅互连层欧姆耦合到衬底中的扩散区域。 后一个区域通常是IGFET的S / D电极。 复合工艺与形成自对准栅极和导电掺杂的多晶硅和衬底区域兼容，同时掺杂相同的杂质。