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    Process for reducing leakage in an integrated circuit with shallow trench isolated active areas
    2.
    发明授权
    Process for reducing leakage in an integrated circuit with shallow trench isolated active areas 有权
    用于减少具有浅沟槽隔离有源区域的集成电路中泄漏的过程

    公开(公告)号：US06817903B1

    公开(公告)日：2004-11-16

    申请号：US09635507

    申请日：2000-08-09

    申请人： Krishnaswamy Ramkumar ,  Kaichiu Wong ,  Venuka Jayatilaka

    发明人： Krishnaswamy Ramkumar ,  Kaichiu Wong ,  Venuka Jayatilaka

    IPC分类号： H01L21311

    CPC分类号： H01L21/02164 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02271 ,  H01L21/31662 ,  H01L21/76205 ,  H01L21/76224

    摘要： A method and process reducing or eliminating electrical leakage between active areas in a semiconductor separated by isolation regions. A method and process are disclosed for the fabrication of an isolation region in a semiconductor. The method and process can be used in the fabrication of isolation regions used for the separation of adjacent active areas in an integrated circuit. A shallow trench is created on the surface of the semiconductor in regions where isolation spaces are to be formed. A layer of silicon dioxide (LINOX) is then grown over the surfaces of the trench. The LINOX covers roughened regions formed along the surfaces of the trench during its formation. The LINOX is then annealed at a temperature above the LINOX deposition temperature for a period of time. Annealing reduces stresses in the LINOX and in the surrounding semiconductor material. Annealing also increases the density of the LINOX. Thus annealing increases the LINOX resistance to gouge during subsequent processing. This leads to a reduction in dislocations in the semiconductor and a reduction in electrical leakage around the isolation region. A more robust LINOX and a reduction in electrical leakage around an isolation region allows the further shrinkage of integrated circuit dimensions. Furthermore, denuding and gettering of the semiconductor are both accomplished during the annealing step which results in a shortening of total processing time. Finally, since gouging of the LINOX no longer occurs where poly/spacer etch overlaps an active area corner, restrictions on placement of poly lines have been eliminated.

    摘要翻译： 一种减少或消除由隔离区隔开的半导体的有源区之间的漏电的方法和过程。 公开了用于制造半导体中的隔离区域的方法和工艺。 该方法和过程可用于制造用于在集成电路中分离相邻有源区的隔离区。 在要形成隔离空间的区域中，在半导体的表面上形成浅沟槽。 然后在沟槽的表面上生长一层二氧化硅（LINOX）。 LINOX包括在其形成期间沿着沟槽的表面形成的粗糙区域。 然后将LINOX在高于LINOX沉积温度的温度下退火一段时间。 退火降低了LINOX和周围半导体材料的应力。 退火也增加了LINOX的密度。 因此，退火在后续加工过程中增加了LINOX电阻。 这导致半导体中位错的减少和隔离区周围的漏电减少。 更强大的LINOX和隔离区域周围的漏电减少允许集成电路尺寸进一步收缩。 此外，半导体的剥蚀和吸杂都在退火步骤期间完成，这导致总处理时间的缩短。 最后，由于在多层/间隔层蚀刻与有源区域角重叠的情况下，LINOX的刨削不再发生，所以已经消除了对多线的布置的限制。

    Isolation technology for submicron semiconductor devices
    4.
    发明授权
    Isolation technology for submicron semiconductor devices 失效
    亚微米半导体器件的隔离技术

    公开(公告)号：US06727161B2

    公开(公告)日：2004-04-27

    申请号：US09505737

    申请日：2000-02-16

    申请人： Yongchul Ahn ,  Kaichiu Wong

    发明人： Yongchul Ahn ,  Kaichiu Wong

    IPC分类号： H01L2176

    CPC分类号： H01L21/76232

    摘要： A process for making a semiconductor structure, includes forming a second dielectric layer on exposed regions of an intermediate structure. The intermediate structure includes: a semiconductor substrate having the regions, a first dielectric layer on at least a first portion of the semiconductor substrate, an etch-stop layer on at least a second portion of the first dielectric layer, and spacers on at least a third portion of said semiconductor substrate. The spacers are adjacent edges of the etch-stop layer and adjacent the exposed regions.

    摘要翻译： 一种制造半导体结构的方法，包括在中间结构的暴露区域上形成第二介电层。 中间结构包括：具有这些区域的半导体衬底，在半导体衬底的至少第一部分上的第一介电层，在第一介电层的至少第二部分上的蚀刻停止层，以及至少 所述半导体衬底的第三部分。 间隔物是蚀刻停止层的相邻边缘并且与暴露区域相邻。

    Contact structure and method of forming a contact structure
    5.
    发明授权
    Contact structure and method of forming a contact structure 有权
    形成接触结构的接触结构和方法

    公开(公告)号：US06596466B1

    公开(公告)日：2003-07-22

    申请号：US09491044

    申请日：2000-01-25

    申请人： Oliver Pohland ,  Kaichiu Wong

    发明人： Oliver Pohland ,  Kaichiu Wong

    IPC分类号： G03F900

    CPC分类号： G03F1/36 ,  H01L21/0334 ,  H01L21/31144 ,  H01L21/76816 ,  H01L27/11 ,  H01L27/1104

    摘要： Contact structures, methods for forming contact structures, and masks for forming contact structures are disclosed. According to one embodiment a contact hole (208) may be formed with a contact hole mask (106/106′) that may have a generally rectangular shape and include corner extensions (108-0 to 108-3) and side indents (110-0 to 110-3). A long side of a contact hole (208) may be aligned in the same direction as an active area (204). A contact hole (208) may be situated between a first portion (206-0) and a second portion (206-1) of an intermediate structure (206). Alternate embodiments can include a “cactus” shaped intermediate structure (406) that may be formed with an intermediate structure mask having corner indents (308).

    摘要翻译： 公开了接触结构，用于形成接触结构的方法和用于形成接触结构的掩模。 根据一个实施例，接触孔（208）可以形成有可以具有大致矩形形状的接触孔掩模（106/106'），并且包括角部延伸部（108-0至108-3）和侧面凹口（110- 0〜110-3）。 接触孔（208）的长边可以在与有效区域（204）相同的方向上对准。 接触孔（208）可以位于中间结构（206）的第一部分（206-0）和第二部分（206-1）之间。 替代实施例可以包括可以形成有具有拐角凹口（308）的中间结构掩模的“仙人掌”形中间结构（406）。

    Methods of forming semiconductor structures, and articles and devices formed thereby
    7.
    发明授权
    Methods of forming semiconductor structures, and articles and devices formed thereby 有权
    形成半导体结构的方法以及由此形成的制品和装置

    公开(公告)号：US06770566B1

    公开(公告)日：2004-08-03

    申请号：US10151127

    申请日：2002-05-16

    申请人： Yongchul Ahn ,  Kaichiu Wong

    发明人： Yongchul Ahn ,  Kaichiu Wong

    IPC分类号： H01L21302

    CPC分类号： H01L21/32131 ,  H01L21/31116

    摘要： A method of forming a semiconductor structure is described that includes etching a first metal layer at the bottom of a via in a first insulating layer to expose a second metal layer, wherein the first metal layer is on the second metal layer, and wherein the etching of the first metal layer is not reactive-ion etching. Methods of making semiconductor devices and electronic devices are also described.

    摘要翻译： 描述了一种形成半导体结构的方法，其包括在第一绝缘层中蚀刻通孔底部的第一金属层以暴露第二金属层，其中第一金属层在第二金属层上，并且其中蚀刻 的第一金属层不是反应离子蚀刻。 还描述了制造半导体器件和电子器件的方法。

    Structure and method for monitoring a semiconductor process, and method of making such a structure
    8.
    发明授权
    Structure and method for monitoring a semiconductor process, and method of making such a structure 有权
    用于监测半导体工艺的结构和方法，以及制造这种结构的方法

    公开(公告)号：US06808944B1

    公开(公告)日：2004-10-26

    申请号：US09621717

    申请日：2000-07-24

    申请人： Bo Jin ,  Kaichiu Wong

    发明人： Bo Jin ,  Kaichiu Wong

    IPC分类号： G01R3126

    CPC分类号： H01L22/34

    摘要： According to one embodiment, a structure for monitoring a process step may include an etch stop layer (102) formed on a substrate (104) and a trench emulation layer (106) formed over an etch stop layer (102). Monitor trenches (108) may be formed through a trench emulation layer (106) that terminate at an etch stop layer (102). Monitor trenches (108) may have a depth equal to a trench emulation layer (106) thickness. A trench emulation layer (106) thickness may be subject to less variation than a substrate trench depth. A monitor structure (100) may thus be used to monitor features formed by one or more process steps that may vary according to trench depth. Such process steps may include a shallow trench isolation insulator chemical mechanical polishing step. In addition, or alternatively, a monitor structure (100) may be formed on a non-semiconductor-on-insulator (SOI) wafer, but include SOI features, providing a less expensive alternative to monitoring some SOI process steps.

    摘要翻译： 根据一个实施例，用于监测处理步骤的结构可以包括形成在衬底（104）上的蚀刻停止层（102）和形成在蚀刻停止层（102）上的沟槽仿真层（106）。 监测沟槽（108）可以通过终止在蚀刻停止层（102）处的沟槽仿真层（106）形成。 监视器沟槽（108）可以具有等于沟槽仿真层（106）厚度的深度。 沟槽仿真层（106）的厚度可能受到比衬底沟槽深度更小的变化。 因此，监视器结构（100）可用于监视由根据沟槽深度而变化的一个或多个处理步骤形成的特征。 这种工艺步骤可以包括浅沟槽隔离绝缘体化学机械抛光步骤。 另外或者替代地，可以在非半导体绝缘体（SOI）晶片上形成监视器结构（100），但是包括SOI特征，为监视一些SOI工艺步骤提供了较便宜的替代方案。

    Soft error resistant memory cell and method of manufacture
    10.
    发明授权
    Soft error resistant memory cell and method of manufacture 有权
    耐软存储单元及其制造方法

    公开(公告)号：US07355880B1

    公开(公告)日：2008-04-08

    申请号：US10823529

    申请日：2004-04-13

    申请人： Bo Jin ,  Ahmad Chatila ,  Kaichiu Wong

    发明人： Bo Jin ,  Ahmad Chatila ,  Kaichiu Wong

    IPC分类号： G11C11/24

    CPC分类号： G11C11/4125 ,  H01L27/11 ,  H01L27/1104 ,  Y10S257/903

    摘要： A semiconductor device memory cell (100) can include a built-in capacitor for reducing a soft-error rate (SER). A memory cell (100) can include a first inverter (102) and second inverter (104) arranged in a cross-coupled configuration. A capacitor (110) can be coupled between a first storage node (106) and second storage node (108). A capacitor (110) can be a “built-in” capacitor formed with interconnect wirings utilized to connect memory cell circuit components.

    摘要翻译： 半导体器件存储单元（100）可以包括用于降低软错误率（SER）的内置电容器。 存储单元（100）可以包括以交叉耦合配置布置的第一反相器（102）和第二反相器（104）。 电容器（110）可以耦合在第一存储节点（106）和第二存储节点（108）之间。 电容器（110）可以是形成有用于连接存储器单元电路部件的互连布线的“内置”电容器。