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    TRANSISTOR ARRANGEMENT WITH A LOAD TRANSISTOR AND A SENSE TRANSISTOR
    1.
    发明公开
    TRANSISTOR ARRANGEMENT WITH A LOAD TRANSISTOR AND A SENSE TRANSISTOR 审中-公开

    公开(公告)号：US20240355923A1

    公开(公告)日：2024-10-24

    申请号：US18760559

    申请日：2024-07-01

    申请人： Infineon Technologies Austria AG

    发明人： Gerhard Noebauer

    IPC分类号： H01L29/78 ,  G01R19/00 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40

    CPC分类号： H01L29/7815 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/402 ,  H01L29/407 ,  H01L29/7813 ,  G01R19/0092

    摘要： A transistor arrangement includes a drift and drain region arranged in a semiconductor body and each connected to a drain node, a plurality of load transistor cells each comprising a source region integrated in a first region of the semiconductor body, a plurality of sense transistor cells each comprising a source region integrated in a second region of the semiconductor body, a first source node electrically connected to the source region of each of the plurality of the load transistor cells via a first source conductor, and a second source node electrically connected to the source region of each of the plurality of the sense transistor cells via a second source conductor, a resistance of the second source conductor is different from a resistance of the first source conductor, and the second source conductor comprises an elongated span with a plurality of meanders in which the connection line reverses its direction.

    Method and Circuitry to Apply an Individual DC Offset to Electrodes on a Large-Scale Ion Trap Quantum Computer
    2.
    发明公开
    Method and Circuitry to Apply an Individual DC Offset to Electrodes on a Large-Scale Ion Trap Quantum Computer 审中-公开

    公开(公告)号：US20240355495A1

    公开(公告)日：2024-10-24

    申请号：US18300203

    申请日：2023-04-13

    申请人： Infineon Technologies Austria AG

    发明人： Jens Repp

    IPC分类号： G21K1/00 ,  H03M1/66

    CPC分类号： G21K1/00 ,  H03M1/662

    摘要： A device includes a plurality of digital-to-analog converters (DACs), a multiplexer, a plurality of electrodes including a first electrode, and a plurality of direct current (DC) offset circuits including a first DC offset circuit. At least one of the plurality of electrodes is located along a lane for movement of an ion. The multiplexer has multiple inputs coupled to the plurality of DACs and multiple outputs including a first output. The first output is configured to provide a first voltage. The first DC offset circuit is coupled between the first output and the first electrode. The first DC offset circuit is configured to add a first DC offset voltage to either the first voltage or the first voltage amplified by a first gain. The first DC offset voltage is configurable.

    CONTROL METHOD FOR DUAL ACTIVE BRIDGE CIRCUIT
    5.
    发明公开
    CONTROL METHOD FOR DUAL ACTIVE BRIDGE CIRCUIT 审中-公开

    公开(公告)号：US20240339934A1

    公开(公告)日：2024-10-10

    申请号：US18296920

    申请日：2023-04-06

    申请人： Infineon Technologies Austria AG

    发明人： Yi ZHANG ,  Cheng ZHANG ,  Sanbao SHI

    IPC分类号： H02M3/335 ,  H02M1/00

    CPC分类号： H02M3/33592 ,  H02M1/0064 ,  H02M3/33584

    摘要： A dual active bridge circuit includes a primary side circuit including first high-side transistor and a first low-side transistor electrically coupled at a first node, and an energy transfer inductor coupled to the first node and configured to provide an inductor current based on a voltage differential across the energy transfer inductor. A secondary side circuit includes a second high-side transistor and a second low-side transistor electrically coupled at a second node. A transformer is configured to transfer energy from the primary side circuit to the secondary side circuit based on the inductor current. A controller is configured to drive each of the transistors between respective switching states with a same duty cycle to control the voltage differential across the energy transfer inductor. The same duty cycle is less than 50% such that all of the transistors are simultaneously off for a predetermined interval.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING A SEMICONDUCTOR DEVICE
    6.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240339506A1

    公开(公告)日：2024-10-10

    申请号：US18618518

    申请日：2024-03-27

    申请人： Infineon Technologies Austria AG

    发明人： Michael Hutzler ,  Thomas Ralf Siemieniec ,  Alexander Breymesser

    IPC分类号： H01L29/40 ,  H01L29/78

    CPC分类号： H01L29/407 ,  H01L29/401 ,  H01L29/7813

    摘要： In an exemplary embodiment, a semiconductor device includes a semiconductor substrate having a first major surface, one or more trenches formed in the first major surface and having a base and a side wall extending from the base to the first major surface, and a conductive member arranged in at least one trench of the one or more trenches. The conductive member is spaced apart from the base of the at least one trench by a lower isolating member and from the side wall of the at least one trench by an enclosed cavity located in the at least one trench. The conductive member has a lower face. A peripheral edge of the lower face of the conductive member is located in the cavity and a central portion of the lower face is in contact with the lower isolating member.

    DEVICE FOR CONTROLLING TRAPPED IONS
    9.
    发明公开
    DEVICE FOR CONTROLLING TRAPPED IONS 审中-公开

    公开(公告)号：US20240312663A1

    公开(公告)日：2024-09-19

    申请号：US18605203

    申请日：2024-03-14

    申请人： Infineon Technologies Austria AG

    发明人： Silke Katharina Auchter ,  Alexander Zesar ,  Clemens Rössler ,  Helmut Heinrich Schoenherr

    IPC分类号： G21K1/00

    CPC分类号： G21K1/003

    摘要： A device for controlling trapped ions includes a substrate. A metal layer is disposed over the substrate. An electrode of an ion trap is disposed over the metal layer, the electrode being configured to trap one or more ions in a space above the electrode. An electrical insulator is disposed between the metal layer and the electrode. The electrical insulator has an upper surface facing towards the electrode and a lower surface facing towards the metal layer. An etching rate of the electrical insulator increases along a direction pointing from the upper surface to the lower surface.