公开(公告)号：US09103916B2

公开(公告)日：2015-08-11

申请号：US13462386

申请日：2012-05-02

申请人： Deric W. Waters ,  Jayawardan Janardhanan

发明人： Deric W. Waters ,  Jayawardan Janardhanan

IPC分类号： G01S19/48

CPC分类号： G01S19/48 ,  G01S5/0252 ,  G01S5/0263 ,  G01S5/14 ,  G01S19/03 ,  G01S19/46

摘要： Apparatus and method for positioning a wireless device. In one embodiment, a method for indoor positioning includes determining a reference location of a wireless device, based on satellite positioning, as the device passes between areas of satellite positioning signal reception and satellite positioning signal non-reception. While in the areas of non-reception, signals transmitted by wireless local area network (WLAN) access points (APs) and parameters of motion of the device are measured. Positions of the device are estimated while in the areas of non-reception based on the reference location and the parameters of motion. A positioning grid for positioning is generated based on the signals measured by the wireless device at the estimated positions.

摘要翻译： 用于定位无线设备的装置和方法。 在一个实施例中，一种用于室内定位的方法包括当卫星定位信号接收和卫星定位信号不接收的区域之间经过卫星定位时，确定无线设备的参考位置。 在不接收的区域中，测量由无线局域网（WLAN）接入点（AP）发送的信号和设备的运动参数。 在基于参考位置和运动参数的不接收的区域中估计设备的位置。 基于由无线设备在估计位置测量的信号产生用于定位的定位网格。

公开(公告)号：US08054103B1

公开(公告)日：2011-11-08

申请号：US12909837

申请日：2010-10-22

申请人： Jayawardan Janardhanan ,  Gopalkrishna Ullal Nayak ,  Vikas Kumar Sinha ,  Sujoy Chakravarty ,  Shivaprakash Halagur ,  Somasunder Kattepura Sreenath

发明人： Jayawardan Janardhanan ,  Gopalkrishna Ullal Nayak ,  Vikas Kumar Sinha ,  Sujoy Chakravarty ,  Shivaprakash Halagur ,  Somasunder Kattepura Sreenath

IPC分类号： H03K19/00

CPC分类号： G06F1/12

摘要： A synchronous circuit for clock multiplexing and output-enable is implemented using a pair of logic gates and an output block. Select signals and enable signals with the corresponding logic sense are provided as inputs to the pair of logic gates, which generate respective logic outputs. The output block contains synchronizers clocked by respective input signals, and receives the logic outputs also as inputs. The output block provides a selected one of the input signals as an output, the provision of the selected input signal being accomplished in a synchronous fashion. Enabling and disabling of the output are also performed synchronously.

摘要翻译： 用于时钟复用和输出使能的同步电路使用一对逻辑门和输出块来实现。 选择信号并使具有相应逻辑感的信号被提供作为逻辑门对的输入，这些逻辑门产生相应的逻辑输出。 输出块包含由相应输入信号计时的同步器，并接收逻辑输出作为输入。 输出块提供所选输入信号中的一个作为输出，所选择的输入信号的提供以同步的方式完成。 同时执行启用和禁用输出。

公开(公告)号：US07817747B2

公开(公告)日：2010-10-19

申请号：US11675565

申请日：2007-02-15

申请人： Khurram Waheed ,  Jayawardan Janardhanan ,  Sameh S. Rezeq ,  Robert B. Staszewski ,  Saket Jalan

发明人： Khurram Waheed ,  Jayawardan Janardhanan ,  Sameh S. Rezeq ,  Robert B. Staszewski ,  Saket Jalan

IPC分类号： H04L27/36

CPC分类号： H04L27/368 ,  H03C5/00 ,  H04L7/0029 ,  H04L7/0041 ,  H04L7/005 ,  H04L7/0079 ,  H04L7/02

摘要： A novel apparatus for and method of delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter. The invention provides a fully digital delay alignment mechanism where better than nanosecond alignment is achieved by accounting for processing delays in the digital circuit modules of the transmitter and by the use of programmable delay elements spread across several clock domains. Tapped delay lines compensate for propagation and settling delays in analog elements such as the DCO, dividers, quad switch, buffers, level shifters and digital pre-power amplifier (DPA). A signal correlative mechanism is provided whereby data from the amplitude and phase/frequency modulation paths to be matched is first interpolated and then cross-correlated to achieve accuracy better than the clock domain of comparison. Within the ADPLL portion of the transmitter, precise alignment of reference and direct point injection points in the ADPLL is provded using multiple clock domains, tapped delay lines and clock adjustment circuits.

摘要翻译： 数字极性发射机的幅度和相位/频率调制路径之间的延迟对准的新型装置和方法。 本发明提供了一种全数字延迟对准机构，其通过考虑发射机的数字电路模块中的处理延迟以及通过使用分布在几个时钟域上的可编程延迟元件来实现比纳秒对准更好的方法。 分接延迟线补偿模拟元件（如DCO，分频器，四通道开关，缓冲器，电平移位器和数字预功率放大器（DPA））中的传播和稳定延迟。 提供了一种信号相关机制，其中来自要匹配的幅度和相位/频率调制路径的数据首先被内插，然后进行交叉相关，以获得比时钟域更好的比较。 在发射机的ADPLL部分内，使用多个时钟域，抽头延迟线和时钟调整电路来证明ADPLL中的参考点和直接点注入点的精确对准。

公开(公告)号：US10330491B2

公开(公告)日：2019-06-25

申请号：US13302329

申请日：2011-11-22

申请人： Jayawardan Janardhanan ,  Sandeep Rao ,  Goutam Dutta

发明人： Jayawardan Janardhanan ,  Sandeep Rao ,  Goutam Dutta

IPC分类号： G06F19/00 ,  G01P21/00 ,  G01C22/00 ,  G01C21/18 ,  G06F1/16 ,  G01C21/16 ,  G01C21/20 ,  G01P15/00 ,  G01F15/00

摘要： A system (10) for pedestrian use includes an accelerometer (110) having multiple electronic sensors; an electronic circuit (100) operable to generate a signal stream representing magnitude of overall acceleration sensed by the accelerometer (110), and to electronically correlate a sliding window (520) of the signal stream with itself to produce peaks at least some of which represent walking steps, and further operable to electronically execute a periodicity check (540) to compare different step periods for similarity, and if sufficiently similar then to update (560) a portion of the circuit substantially representing a walking-step count; and an electronic display (190) responsive to the electronic circuit (100) to display information at least in part based on the step count. Other systems, electronic circuits and processes are disclosed.

公开(公告)号：US08411804B2

公开(公告)日：2013-04-02

申请号：US13031257

申请日：2011-02-21

申请人： Karthik Subburaj ,  Anant Shankar Kamath ,  Jayawardan Janardhanan

发明人： Karthik Subburaj ,  Anant Shankar Kamath ,  Jayawardan Janardhanan

IPC分类号： H04L27/06 ,  H04L25/06 ,  H04L25/10 ,  H04L7/00

CPC分类号： H04L25/4902

摘要： A digital PWM demodulator includes a first set of delay cells to receive a PWM signal and to propagate the PWM signal in a forward direction for a first interval. Delayed signals obtained at the end of the first interval are propagated in the reverse direction through the delay cells for a second interval. A logic zero feeds into the last cell at the start of the second interval. The output of a last cell in the delay cells at the end of the second interval is indicative of a data value modulated on the PWM signal. The digital PWM demodulator includes a second set of delay cells designed to operate identical to the first set of delay cells. The first set of delay cells and the second set of delay cells in conjunction with additional digital circuitry demodulate alternate periods of the PWM signal.

摘要翻译： 数字PWM解调器包括第一组延迟单元，用于接收PWM信号并且沿正向方向传播PWM信号第一间隔。 在第一间隔结束时获得的延迟信号通过延迟单元反向传播第二间隔。 逻辑零在第二个间隔开始时馈送到最后一个单元格。 在第二间隔结束时，延迟单元中的最后一个单元的输出表示在PWM信号上调制的数据值。 数字PWM解调器包括被设计为与第一组延迟单元相同的第二组延迟单元。 第一组延迟单元和第二组延迟单元结合附加数字电路解调PWM信号的交替周期。

公开(公告)号：US20120136573A1

公开(公告)日：2012-05-31

申请号：US13301913

申请日：2011-11-22

申请人： Jayawardan Janardhanan ,  Goutam Dutta ,  Varun Tripuraneni

发明人： Jayawardan Janardhanan ,  Goutam Dutta ,  Varun Tripuraneni

IPC分类号： G01C21/16

CPC分类号： G01C21/16 ,  G01C21/165 ,  G01C21/20 ,  G01C22/006

摘要： A user-heading determining system (10) for pedestrian use includes a multiple-axis accelerometer (110) having acceleration sensors; a device-heading sensor circuit (115) physically situated in a fixed relationship to the accelerometer (110); an electronic circuit (100) operable to generate signals representing components of acceleration sensed by the accelerometer (110) sensors, and to electronically process at least some part of the signals to produce an estimation of attitude of a user motion with respect to the accelerometer, and further to combine the attitude estimation (750, α) with a device heading estimation (770, ψ) responsive to the device-heading sensor circuit, to produce a user heading estimation (780); and an electronic display (190) responsive to the electronic circuit (100) to display information at least in part based on the user heading estimation. Other systems, circuits and processes are also disclosed.

摘要翻译： 用于行人使用的用户航向确定系统（10）包括具有加速度传感器的多轴加速度计（110） 物理地位于与所述加速度计（110）固定关系的设备航向传感器电路（115）; 电子电路（100），其可操作以产生表示由所述加速度计（110）传感器感测到的加速度的分量的信号，并且电子处理所述信号的至少一部分以产生相对于所述加速度计的用户运动姿态的估计， 并且进一步将所述姿态估计（750，α）与响应于所述设备航向传感器电路的设备航向估计（770，ψ）组​​合以产生用户航向估计（780）; 以及响应于所述电子电路（100）至少部分地基于所述用户标题估计来显示信息的电子显示器（190）。 还公开了其它系统，电路和过程。

公开(公告)号：US20130021182A1

公开(公告)日：2013-01-24

申请号：US13184570

申请日：2011-07-18

申请人： Vineet Mishra ,  Jayawardan Janardhanan ,  Samala Sreekiran ,  Meghna Agrawal

发明人： Vineet Mishra ,  Jayawardan Janardhanan ,  Samala Sreekiran ,  Meghna Agrawal

IPC分类号： H03M3/02

CPC分类号： H03M3/496 ,  H03M3/39 ,  H03M3/464

摘要： A continuous-time sigma-delta analog to digital converter (CTSD ADC) includes a comparator that samples the time integral of an analog signal at each rising edge and falling edge of a sampling clock. A feedback block, operating as a digital to analog converter, receives the outputs of the comparator and generates corresponding analog signals also at each rising and falling edge of the sampling clock. The feedback blocks are implemented as either switched-resistor or switched-current circuits. High signal-to-noise ratio (SNR) is achieved in the CTSD ADC without the need to use very high sampling clock frequencies. Compensation for excess loop delay is provided using a local feedback technique. In an embodiment, the sigma delta modulator in the CTSD ADC is implemented as a second order loop, and the comparator as a two-level comparator.

摘要翻译： 连续时间Σ-Δ模数转换器（CTSD ADC）包括在采样时钟的每个上升沿和下降沿采样模拟信号的时间积分的比较器。 作为数模转换器工作的反馈块接收比较器的输出，并在采样时钟的每个上升沿和下降沿也产生相应的模拟信号。 反馈块实现为开关电阻或开关电流电路。 在CTSD ADC中实现了高信噪比（SNR），而不需要使用非常高的采样时钟频率。 使用本地反馈技术提供多余回路延迟的补偿。 在一个实施例中，CTSD ADC中的Σ-Δ调制器被实现为二阶环路，比较器被实现为两电平比较器。

公开(公告)号：US20120213314A1

公开(公告)日：2012-08-23

申请号：US13031257

申请日：2011-02-21

申请人： Karthik Subburaj ,  Anant Shankar Kamath ,  Jayawardan Janardhanan

发明人： Karthik Subburaj ,  Anant Shankar Kamath ,  Jayawardan Janardhanan

IPC分类号： H04L27/06

CPC分类号： H04L25/4902

摘要： A digital PWM demodulator includes a first set of delay cells to receive a PWM signal and to propagate the PWM signal in a forward direction for a first interval. Delayed signals obtained at the end of the first interval are propagated in the reverse direction through the delay cells for a second interval. A logic zero feeds into the last cell at the start of the second interval. The output of a last cell in the delay cells at the end of the second interval is indicative of a data value modulated on the PWM signal. The digital PWM demodulator includes a second set of delay cells designed to operate identical to the first set of delay cells. The first set of delay cells and the second set of delay cells in conjunction with additional digital circuitry demodulate alternate periods of the PWM signal.

摘要翻译： 数字PWM解调器包括第一组延迟单元，用于接收PWM信号并且沿正向方向传播PWM信号第一间隔。 在第一间隔结束时获得的延迟信号通过延迟单元反向传播第二间隔。 逻辑零在第二个间隔开始时馈送到最后一个单元格。 在第二间隔结束时，延迟单元中的最后一个单元的输出表示在PWM信号上调制的数据值。 数字PWM解调器包括被设计为与第一组延迟单元相同的第二组延迟单元。 第一组延迟单元和第二组延迟单元结合附加数字电路解调PWM信号的交替周期。

公开(公告)号：US20090252269A1

公开(公告)日：2009-10-08

申请号：US12060886

申请日：2008-04-02

申请人： Sarma S. Gunturi ,  Jawaharlal Tangudu ,  Sthanunathan Ramakrishnan ,  Jayawardan Janardhanan ,  Debapriya Sahu ,  Subhashish Mukherjee

发明人： Sarma S. Gunturi ,  Jawaharlal Tangudu ,  Sthanunathan Ramakrishnan ,  Jayawardan Janardhanan ,  Debapriya Sahu ,  Subhashish Mukherjee

IPC分类号： H04L7/00

CPC分类号： H04L27/362 ,  H04L7/0331

摘要： A method of achieving reduced modulation range requirement in a Digitally Controlled Oscillator (DCO) which is deployed as part of a DRP (Digital Radio Processor) and tuned to a tuning frequency range having operating-channel center-frequencies, wherein phase difference between consecutive samples is termed as FCW (Frequency Control Word), uses the steps of digitally modifying and limiting the FCW so that the FCW does not exceed known FCW thresholds, e.g., chosen from π/2, π/4, π/8, and redistributing the FCWs while maintaining a cumulative sum of phases and without significant EVM (Error Vector Magnitude) degradation. The FCW threshold can be chosen arbitrarily and need not be in the form of π/2n. The method uses a FCW limiting algorithm which reduces supply voltage sensitivity of the DCO and enables significant reduction in area of capacitor bank which would be otherwise needed.

摘要翻译： 一种在数字控制振荡器（DCO）中实现减少的调制范围要求的方法，其被部署为DRP（数字无线电处理器）的一部分并被调谐到具有操作信道中心频率的调谐频率范围，其中连续样本之间的相位差 被称为FCW（频率控制字），使用数字修改和限制FCW的步骤，使得FCW不超过已知的FCW阈值，例如从pi / 2，pi / 4，pi / 8选择并重新分配 FCW同时保持相位的累积和，并且没有显着的EVM（误差矢量幅度）劣化。 FCW阈值可以任​​意选择，不需要以pi / 2n的形式。 该方法使用FCW限制算法，其降低DCO的电源电压灵敏度，并且能够显着减小电容器组的面积，否则将需要它。

公开(公告)号：US20070189417A1

公开(公告)日：2007-08-16

申请号：US11675565

申请日：2007-02-15

申请人： Khurram Waheed ,  Jayawardan Janardhanan ,  Sameh S. Rezeq ,  Robert B. Staszewski ,  Saket Jalan

发明人： Khurram Waheed ,  Jayawardan Janardhanan ,  Sameh S. Rezeq ,  Robert B. Staszewski ,  Saket Jalan

IPC分类号： H04L27/04 ,  H04L7/00

CPC分类号： H04L27/368 ,  H03C5/00 ,  H04L7/0029 ,  H04L7/0041 ,  H04L7/005 ,  H04L7/0079 ,  H04L7/02

摘要： A novel apparatus for and method of delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter. The invention provides a fully digital delay alignment mechanism where better than nanosecond alignment is achieved by accounting for processing delays in the digital circuit modules of the transmitter and by the use of programmable delay elements spread across several clock domains. Tapped delay lines compensate for propagation and settling delays in analog elements such as the DCO, dividers, quad switch, buffers, level shifters and digital pre-power amplifier (DPA). A signal correlative mechanism is provided whereby data from the amplitude and phase/frequency modulation paths to be matched is first interpolated and then cross-correlated to achieve accuracy better than the clock domain of comparison. Within the ADPLL portion of the transmitter, precise alignment of reference and direct point injection points in the ADPLL is provded using multiple clock domains, tapped delay lines and clock adjustment circuits.

摘要翻译： 数字极性发射机的幅度和相位/频率调制路径之间的延迟对准的新型装置和方法。 本发明提供了一种全数字延迟对准机制，其通过考虑发射机的数字电路模块中的处理延迟以及通过使用分布在几个时钟域上的可编程延迟元件来实现比纳秒对准更好的方法。 分接延迟线补偿模拟元件（如DCO，分频器，四通道开关，缓冲器，电平移位器和数字预功率放大器（DPA））中的传播和稳定延迟。 提供了一种信号相关机制，其中来自要匹配的幅度和相位/频率调制路径的数据首先被内插，然后进行交叉相关，以获得比时钟域更好的比较。 在发射机的ADPLL部分内，使用多个时钟域，抽头延迟线和时钟调整电路来证明ADPLL中的参考点和直接点注入点的精确对准。